Proceedings Third IEEE Real-Time Technology and Applications Symposium
DOI: 10.1109/rttas.1997.601360
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OS-controlled cache predictability for real-time systems

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Cited by 124 publications
(116 citation statements)
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“…We reserved cache partitions 0-7 (CBM bitmask 0×000FF) to CPU1 and partitions 8-15 (CBM bitmask 0×0FF00) to CPU2. We flushed the entire cache initially, and mitigated potential interference to CPU1 and CPU2 by moving all system services to the remaining cores and assigning to them the remaining partitions (partitions [16][17][18][19]. We created a periodic task that sequentially accesses a 4MB array.…”
Section: Cache Lookup Controlmentioning
confidence: 99%
See 1 more Smart Citation
“…We reserved cache partitions 0-7 (CBM bitmask 0×000FF) to CPU1 and partitions 8-15 (CBM bitmask 0×0FF00) to CPU2. We flushed the entire cache initially, and mitigated potential interference to CPU1 and CPU2 by moving all system services to the remaining cores and assigning to them the remaining partitions (partitions [16][17][18][19]. We created a periodic task that sequentially accesses a 4MB array.…”
Section: Cache Lookup Controlmentioning
confidence: 99%
“…Existing work in this domain relies on software-based solutions, such as page coloring [17], for cache partitioning. Most previous solutions focus on improving the average performance of the system (e.g., [10,11,24]) and thus are not suitable for real-time systems that require worst-case performance guarantees.…”
Section: Introductionmentioning
confidence: 99%
“…Kaseridis et al [11] propose bandwidth-aware memory sub-system management for avoiding resource contention. Various approaches are also proposed to manage LLC [5,8,14,15,20,31,32,33,34]. In particular, Qureshi et al [32] design a utility-based cache partitioning scheme that allocates appropriate cache resources based on application miss rate monitored through dedicated hardware.…”
Section: Related Workmentioning
confidence: 99%
“…These works deals only with fixed priority schedulers. Other works try to eliminate or reduce the inter-task interference by using hardware and software techniques [7][8][9][10], but they do not face the intrinsic interference problem. Additionally, in some cases, the extrinsic interference is only reduced, and therefore, the predictability problem of the cache-related preemption delay remains unresolved.…”
Section: Introductionmentioning
confidence: 99%