Oscillatory patterns in heart rate variability and complexity: A meta-analysis

Natali, J; Starzynski, Paulo Nogueira; Chauí‐Berlinck, José Guilherme

doi:10.1016/j.bspc.2016.11.012

Cited by 4 publications

(1 citation statement)

References 28 publications

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“…In line with standards on HRV previously published [17], Additionally, SD1, SD2, and the ratio SD1/SD2 were calculated for nonlinear measurements.…”

Section: Feature Extractionmentioning

confidence: 99%

Hardware-Accelerated Neural Network Model for Early Prediction of Sudden Cardiac Arrest Based on Heart Rate Variability Metrics

Pan,

Nguyen,

Chao

2024

Preprint

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Sudden Cardiac Arrest (SCA) constitutes a dire medical condition, marked by the abrupt cessation of effective blood circulation due to the heart's failure to contract properly. This leads to acute circulatory collapse, often culminating in loss of consciousness within an hour and potentially resulting in fatality within minutes if left unattended. Heart rate variability (HRV) serves as a critical biometric, derived from electrocardiogram (ECG) signals through QRS wave detection algorithms that calculate the R-R Intervals (RRI). These intervals provide the basis for extracting various characteristics of cardiac rhythm, encompassing time-domain, frequency-domain, and nonlinear features. This study presents a neural network-based classification algorithm that leverages HRV metrics to categorize patients into SCA and Normal Sinus Rhythm (NSR) cohorts. Utilizing k-fold cross-validation, the devised neural network (NN) model demonstrated a predictive accuracy of 87.88%, a sensitivity of 88.89%, and a specificity of 87.87% in preemptively identifying SCA up to 55 minutes prior to occurrence. In order to harness the benefits of hardware acceleration, the algorithm is instantiated on a Field-Programmable Gate Array (FPGA). Its computational efficiency is subsequently benchmarked against traditional software-based methodologies. The hardware-level implementation is made possible in Verilog HDL and was verified successfully with expected performance by Register-Transfer Level (RTL) simulation via Vivado 2020.2.

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“…In line with standards on HRV previously published [17], Additionally, SD1, SD2, and the ratio SD1/SD2 were calculated for nonlinear measurements.…”

Section: Feature Extractionmentioning

confidence: 99%

Hardware-Accelerated Neural Network Model for Early Prediction of Sudden Cardiac Arrest Based on Heart Rate Variability Metrics

Pan,

Nguyen,

Chao

2024

Preprint

View full text Add to dashboard Cite

show abstract

Hardware-accelerated neural network model for early prediction of sudden cardiac arrest based on heart rate variability metrics

Pan,

Nguyen,

Chao

2024

Microsyst Technol

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Sudden Cardiac Arrest (SCA) constitutes a dire medical condition, marked by the abrupt cessation of effective blood circulation due to the heart's failure to contract properly. This leads to acute circulatory collapse, often culminating in loss of consciousness within an hour and potentially resulting in fatality within minutes if left unattended. Heart rate variability (HRV) serves as a critical biometric, derived from electrocardiogram (ECG) signals with ventricular depolarization waves to further calculate the R-R Intervals (RRIs). These intervals provide the basis for extracting various characteristics of cardiac rhythm, encompassing time-domain, frequency-domain, and nonlinear features. This study presents a neural network-based classification algorithm that leverages HRV metrics to categorize patients into SCA and Normal Sinus Rhythm (NSR) cohorts. The proposed neural network (NN) model showcased impressive results, achieving an accuracy of 96.23%, a sensitivity of 94.35%, and a specificity of 98.12% in detecting SCA, as evaluated through leave-one-subject-out analysis. In order to harness the benefits of hardware acceleration, the algorithm is implemented on a Field-Programmable Gate Array (FPGA). Its computational efficiency is subsequently benchmarked against traditional software-based methodologies. The hardware-level implementation is made possible in Verilog hardware description language (HDL) and was verified successfully with expected performance by register-transfer level (RTL) simulation via Vivado 2020.2.

show abstract