Output load capacitance based low power implementation of UART on FPGA

Singh, Prabhat Ranjan; Pandey, Bishwajeet; Kumar, Tanesh; Das, Teerath; Pandey, Om Jee

doi:10.1109/iccci.2014.6921826

Cited by 16 publications

(9 citation statements)

References 11 publications

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“…P R Singh et.al. [12] In this work, it achieved 99.72% reduction in IOs power consumption of Universal Asynchronous Receiver Transmitter (UART) if it scaled down output load from 10,000pf to 5pF in IOB setting of FPGA. Universal Asynchronous Receiver and Transmitter are a transceiver circuits that transmit/receive data between parallel and serial forms and vice versa.…”

Section: Dr Garima Bandhawarkar Wakhle Et Al [4]mentioning

confidence: 99%

VHDL Implementation of Universal Asynchronous Receiver Transmitter with Linear Feedback Shift Register

Singh¹,

Kaur²

2017

IJARCSSE

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Abstract-UART hardware are controlled by a clock signal which runs at a multiple of the data rate, typically 8 times the bit rate. The receiver tests the state of the incoming signal on each clock pulse, looking for the beginning of the start bit. If the apparent start bit lasts at least one-half of the bit time, it is valid and signals the start of a new character.In this paper review the different method of uart transmission and receiver

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Section: Dr Garima Bandhawarkar Wakhle Et Al [4]mentioning

confidence: 99%

VHDL Implementation of Universal Asynchronous Receiver Transmitter with Linear Feedback Shift Register

Singh¹,

Kaur²

2017

IJARCSSE

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“…Authors designed an energy-efficient Arithmetic Logic Unit (ALU) by varying the frequency of FPGA which reduces clock and dynamic power consumption [17]. A low power UART is developed by authors by varying the output load capacitance over Virtex-6 FPGA [18]. A power-efficient FIR filter is designed by authors for wireless network sensors as pre signal processing step using FPGA [19].…”

Section: Related Workmentioning

confidence: 99%

Frequency Scaling Based Power Efficient Current Source Design on FPGA

Kaur,

Kumar,

Gandhi

et al. 2019

IJEAT

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 Abstract: Power deficiency is one of the major problems that the whole world is facing now. This is happening because of the immense increase in the world's population and the global increase of industrialization. So in order to minimize the consumption of power, an energy efficient current source is designed with the help of Field Programmable Gate Array (FPGA). This work gives light on how the power variation takes place in a current source with an increase in frequency value. In this research work, the current source is implemented on 28 nanometers (nm) Airtx-7 FPGA. The work is demonstrated on Xilinx 14.1 ISE simulator. VHSIC Hardware Description Language (VHDL) is used for writing the code of current source. The frequency of current source with Airtx-7 FPGA is increased from 100MHz to 5GHz. It is analyzed that the total power consumption is less as the value of frequency is low. So it is always advisable to operate the device at a lower frequency range in orderto save more energy.

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“…Capacitance scaling is one of the best energy efficient technique for FPGA based VLSI design. Earlier capacitance scaling is also used to design of energy efficient ROM [12], energy efficient UART [13] and power optimized register [14]. Here we are going to utilize the benefit of capacitance scaling for this Vedic Divider based on Vedic formula of Parvartya Yojayet.…”

Section: Fig 2 List Of Vedic Formula (Sutra) In Vedic Mathematicsmentioning

confidence: 99%

Capacitance Scaling Based Energy Efficient Vedic Divider using Paravartya Yojayet on 28nm FGPA

Madhok¹,

Goswami²,

Kumar³

2016

GJET

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In this paper, we have designed an energy efficient Vedic Divider using an ancient Vedic mathematics technique known as "ParavartyaYojayet". Para-vartyaYojayet is a Sanskrit name which means transpose and adjust. Vedic mathematical formulas are used to solve tedious and cumbersome arithmetic operations. Today's world demands implementation of techniques which take lesser time and are energy efficient so we have designed a Vedic divider to solve long divisions in seconds. Our design consists of 2 inputs for dividend and divisor and 2 outputs that are remainder and quotient. Many researchers have done research work on Vedic mathematics to solve DSP operations using Urdhava-Triyagbhayam multiplication sutra, to design asynchronous Vedic DSP processor core and lots more. In our paper we have implemented our code on Xilinx ISE Design Suite 14.2 and results were tested on 28nm FPGA platform. We have done power analysis by varying frequencies and capacitance to make our Vedic divider energy efficient. Analysis results that the maximum power is consumed at 2.2GHz and minimum power is consumed at 1.2GHz. In respect of capacitance maximum power is consumed at 100pF and minimum power is consumed at 20pF.Step 3: We minus divisor 12 from 10 and get -2. Multiply this -2 by first digit of 25 i.e.2 and we finally get -4 and add -4 to 25 and get 21 as quotient as shown in Figure 6. Fig. 7. RTL Schematic of Parvartya Yojayet: Part IIStep 4: Take Mod of 21 and 10 and multiply 1 (i.e.21%10) with -2 and add final result -2 in remainder 4 (in step 1) and final remainder is 2 as shown in Figure 7.

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Output load capacitance based low power implementation of UART on FPGA

Cited by 16 publications

References 11 publications

VHDL Implementation of Universal Asynchronous Receiver Transmitter with Linear Feedback Shift Register

VHDL Implementation of Universal Asynchronous Receiver Transmitter with Linear Feedback Shift Register

Frequency Scaling Based Power Efficient Current Source Design on FPGA

Capacitance Scaling Based Energy Efficient Vedic Divider using Paravartya Yojayet on 28nm FGPA

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