Output transition time modeling of CMOS structures

Maurine, Philippe; Rezzoug, M.; Auvergne, D.

doi:10.1109/iscas.2001.922060

Cited by 9 publications

(30 citation statements)

References 16 publications

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“…In [12][13][14][15], OUT,slow was shown to increase proportionally to √ in , as was confirmed by simulations on 0.18-m and 0.13-m technologies. In [12][13][14][15], this dependence was found by assuming a triangular waveform for the current that a logic gate draws from the supply.…”

Section: Evaluation Of Outslowsupporting

confidence: 54%

“…Fundamentally, the model in [12][13][14][15] is based on a separate analysis of the output transition time under fast and slow inputs, as depicted in Figure 1 the output transition time OUT is well known to increase as depicted in Figure 1. Thus, OUT must be modeled with a different expression OUT,slow that increases as in increases, which is found to be proportional to √ in according to [12][13][14][15]. Unfortunately, this model is affected by a very low accuracy in nanometer technologies.…”

Section: Model Inmentioning

confidence: 99%

“…Instead of following the circuit analysis approach in [12][13][14][15] based on the simple (but unrealistic) case of = 1, it is preferable to follow a different approach, in order to achieve an adequate accuracy. Indeed, in general parameter OUT,fast can be modeled as…”

Section: Evaluation Of Outfastmentioning

confidence: 99%

“…As was suggested in [12][13][14][15] the proposed model is split into two analytical expressions that respectively hold for fast and slow inputs. The analytical expression under fast inputs is found from a transient circuit analysis and general considerations on the transition time dependencies.…”

Section: Introductionmentioning

confidence: 99%

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Simple and accurate modeling of the output transition time in nanometer CMOS gates

Alioto

Palumbo

Poli

2010

Circuit Theory & Apps

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In this paper, a model of the output transition time on nanometer CMOS gates is proposed. The development of this model follows the general approach used by Auvergne in (IEE Electron. Lett. separately models the output transition time under fast and slow inputs. The proposed model is based on a combined transient and DC circuit analysis, and requires a few simulations. This approach allows for strongly reducing the number of required parameters and simulations compared with other models proposed in the literature.The analytical model proposed is very simple and has a clear physical meaning, thereby allowing an efficient implementation in CAD tools performing timing analysis, as well as an easy scalability through different processes and technology generations. Spectre simulations on a 65 nm CMOS technology and the 45, 32, 22 nm Berkeley Predictive Technology Models (BPTM) [Berkeley Predictive Technology Model (BPTM). ONLINE@11/25/2008: http://www.eas.asu.edu/∼ptm/] show that the model accuracy is the same as the state-of-the-art models, with an average error of only 4%. Comparison with currently used table-based models showed also a significant reduction in the CPU time needed to simulate and characterize CMOS logic gates.

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Section: Evaluation Of Outslowsupporting

confidence: 54%

Section: Model Inmentioning

confidence: 99%

Section: Evaluation Of Outfastmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Simple and accurate modeling of the output transition time in nanometer CMOS gates

Alioto

Palumbo

Poli

2010

Circuit Theory & Apps

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“…This scheme is applicable for CAD tools requiring accuracy as well as fast computation time. There has been much research done on developing closedform expression [1][2] [4][7] [9]. Ko and Balsara proposed a gate-sizing technique for reducing overall power dissipation on non-critical paths [6].…”

Section: Introductionmentioning

confidence: 99%

Buffer sizing for minimum energy-delay product by using an approximating polynomial

Kang

Abbaspour

Pedram

2003

Proceedings of the 13th ACM Great Lakes Symposium on VLSI - GLSVLSI '03

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This paper first presents an accurate and efficient method of estimating the short circuit energy dissipation and the output transition time of CMOS buffers. Next, the paper describes a sizing method for tapered buffer chains. It is shown that the first-order sizing behavior, which considers only the capacitive energy dissipation, can be improved by considering the shortcircuit dissipation as well, and that the second-order polynomial expressions for short-circuit energy improves the accuracy over linear expressions. These results are used to derive sizing rules for buffered chains, which optimize the overall energy-delay product.

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Structure Independent Representation of Output Transition Time for CMOS Library

Maurine

Azémard

Auvergne

2002

Lecture Notes in Computer Science

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Non zero signal rise and fall times significantly contribute to the gate propagation delay. Designers must accurately consider them when defining timing library format. Based on a design oriented macro-model of the timing performance of CMOS structures, we present in this paper a general representation of transition times allowing fast and accurate cell performance evaluation. This general representation is then exploited to define a robust characterization protocol of the output transition time of standard cells. Both the representation and the protocol are finally validated comparing calculated gate input-output transition time values with standard look-up representation obtained from Hspice simulations (Bsim3v.3, level 69, 0.25mm process).

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Output transition time modeling of CMOS structures

Cited by 9 publications

References 16 publications

Simple and accurate modeling of the output transition time in nanometer CMOS gates

Simple and accurate modeling of the output transition time in nanometer CMOS gates

Buffer sizing for minimum energy-delay product by using an approximating polynomial

Structure Independent Representation of Output Transition Time for CMOS Library

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