2020
DOI: 10.35848/1882-0786/aba22c
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Over 1% magnetoresistance ratio at room temperature in non-degenerate silicon-based lateral spin valves

Abstract: To augment the magnetoresistance (MR) ratio of n-type non-degenerate Si-based lateral spin valves (Si-LSVs), we modify the doping profile in the Si layer and introduce a larger local strain into the Si channel by changing a capping insulator. The highest MR ratio of 1.4% is achieved in the Si-LSVs through these improvements, with significant roles played by a reduction in the resistance-area product of the ferromagnetic contacts and an enhancement of the momentum relaxation time in the Si channel.

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Cited by 10 publications
(4 citation statements)
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“…The Au–Si and/or Au-Al-Si liquid phases diffuse mainly along the AlN/Si interface (Fig. 3 i) due to the strong tensile strain 29 , and the interface is more susceptible to destruction than the other areas. Finally, Au reaches the FM electrodes and invades the MgO tunnelling barrier.…”
Section: Resultsmentioning
confidence: 99%
“…The Au–Si and/or Au-Al-Si liquid phases diffuse mainly along the AlN/Si interface (Fig. 3 i) due to the strong tensile strain 29 , and the interface is more susceptible to destruction than the other areas. Finally, Au reaches the FM electrodes and invades the MgO tunnelling barrier.…”
Section: Resultsmentioning
confidence: 99%
“…The Au-Si and/or Au-Al-Si liquid phases diffuse mainly along the AlN/Si interface (Fig. 3h) due to the strong tensile strain 27 , and the interface is more susceptible to destruction than the other areas. Finally, Au reaches the FM electrodes and invades the MgO tunnelling barrier.…”
Section: Figures 2a and 2b Show Optical Microscopy Images Of Sample Amentioning
confidence: 99%
“…Many studies have been conducted to realize spin transistors; however, the performance of the present devices is far from the level for realistic applications. A magnetoresistance (MR) ratio of more than 100% is required, but the highest MR ratio reported thus far is ≈1% (1.4% at room temperature [ 14 ] and 0.12% at 8 K [ 15 ] ) for Si‐based devices and ≈10% for III–V semiconductor‐based devices when measured under a constant‐voltage condition at ≈1.4 K (or 80% under a constant‐current condition with Esaki‐diode tunneling contacts). [ 9 ] In theory, to obtain a large MR ratio, the contact resistance of FM electrode/nonmagnetic semiconductor interfaces needs to be adjusted within a narrow window.…”
Section: Introductionmentioning
confidence: 99%