Overcoming Early-Life Failure and Aging for Robust Systems

Li, Yanjing; Kim, Young Moon; Mintarno, Evelyn; Gardner, Donald S.; Mitra, Subhasish

doi:10.1109/mdt.2009.152

Cited by 61 publications

(11 citation statements)

References 11 publications

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“…Simulation results in Section IV take those non-idealities into account, derive design guidelines to maximize PRTA benefits, and demonstrate that PRTA is highly beneficial for systems that experience workload with low stress probability characteristics. Real-time aging information for PRTA can be obtained (or calibrated) from a variety of sources: 1) on-chip ring oscillators or other canary equivalent circuits [27]- [32]; 2) on-chip sensors such as temperature sensors (by predicting aging based on temperature profiles and assuming worst-case workload profiles) [33]- [36]; 3) delay shift detectors [11], [21], [37]; 4) on-line self-test and self-diagnostics [38]- [40]; and 5) indirectly measuring degradation by adjusting selftuning parameters until failure occurs.…”

Section: Progressive-real-time-aging-assisted (Prta)mentioning

confidence: 99%

Self-Tuning for Maximized Lifetime Energy-Efficiency in the Presence of Circuit Aging

Mintarno

Skaf

Zheng

et al. 2011

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-This paper presents an integrated framework, together with control policies, for optimizing dynamic control of self-tuning parameters of a digital system over its lifetime in the presence of circuit aging. A variety of self-tuning parameters such as supply voltage, operating clock frequency, and dynamic cooling are considered, and jointly optimized using efficient algorithms described in this paper. Our optimized self-tuning approach satisfies performance constraints at all times, and maximizes a lifetime computational power efficiency (LCPE) metric, which is defined as the total number of clock cycles achieved over lifetime divided by the total energy consumed over lifetime. We present three control policies: 1) progressive-worst-case-aging (PWCA), which assumes worst-case aging at all times; 2) progressive-on-stateaging (POSA), which estimates aging by tracking active/sleep modes, and then assumes worst-case aging in active mode and long recovery effects in sleep mode; and 3) progressive-real-timeaging-assisted (PRTA), which acquires real-time information and initiates optimized control actions. Various flavors of these control policies for systems with dynamic voltage and frequency scaling (DVFS) are also analyzed. Simulation results on benchmark circuits, using aging models validated by 45 nm measurements, demonstrate the effectiveness and practicality of our approach in significantly improving LCPE and/or lifetime compared to traditional one-time worst-case guardbanding. We also derive system design guidelines to maximize self-tuning benefits.Index Terms-Adaptive supply voltage and clock frequency, circuit aging, energy-efficiency, lifetime reliability.

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Section: Progressive-real-time-aging-assisted (Prta)mentioning

confidence: 99%

Self-Tuning for Maximized Lifetime Energy-Efficiency in the Presence of Circuit Aging

Mintarno

Skaf

Zheng

et al. 2011

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…The lifetime of an IC includes three parts from tape-out to discard as useless, i.e. early lifetime, normal lifetime and aging [1]. In normal lifetime, soft error is the main factor impacting circuit reliability and in nanoscale technology the impacting factor is becoming more serious [2].…”

Section: Introductionmentioning

confidence: 99%

A transient pulse dually filterable and online self-recoverable latch

Yan

Liang

et al. 2017

IEICE Electron. Express

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This paper presents a transient Pulse Dually Filterable and online Self-Recoverable (referred to as PDFSR) latch. Based on soft error masking property of C-element and using built-in delayed paths combined with a Schmitt inverter, a single event transient (SET) pulse could be dually filtered. Meanwhile, mutually feeding back mechanism of multiple C-elements was constructed to retain data, which makes the latch self-recoverable from a single event upset (SEU). Simulation results have demonstrated the SET filtering ability and SEU resilience at the cost of only 2.0% area-powerdelay-width product increase on average, compared with the similar latches.

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“…On-line self-test and diagnostics allow a system to test itself concurrently during normal operation [2]- [4]. Software-based inference methods [5]- [7] use softwareimplemented test operations to capture variation and detect errors.…”

Section: Introductionmentioning

confidence: 99%

Accurate and inexpensive performance monitoring for variability-aware systems

Lai

Gupta

2014

2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC)

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Abstract-Designing reliable integrated systems has become a major challenge with shrinking geometries, increasing fault rates and devices which age substantially in their usage life. The proposed research is motivated by the observation that many of the in-field failures are delay failures and several variability signatures are also delay-related. The origins of temporal delay fluctuations include manufacturing variability, voltage/temperature changes, negative or positive bias temperature instability-related Vth degradation, etc. Since the actual delay changes depend on process variations as well as workload, onchip monitoring may be the best way of predicting them. There is a need to monitor circuit performance during manufacturing as well as at runtime to predict achievable performance and warn against impending failures. Adaptive mechanisms in hardware and/or software can optimize the trade-off between errors, energy and performance based on the feedback from runtime circuit performance monitors. This paper presents approaches for automated synthesis of design-dependent performance monitors. These monitors can be used to predict impending delay failures relatively inexpensively. For low-overhead monitoring, we propose multiple designdependent ring oscillators (DDROs) as smart canary structures which can reliably predict achievable chip frequency but with margins for local variations. Early silicon results indicate that DDROs can reduce delay monitoring error by 35% compared to conventional ring oscillators. To further improve the prediction (albeit at a higher overhead), we propose in-situ slack monitors (SlackProbe) which can match local variations as well at overheads much smaller than monitoring all sequential elements. SlackProbe reduces the number of monitors required by over 15X with 5% additional delay margin in several commercial processor benchmarks. Finally, we show an example of software testbed that demonstrates a variability-aware system that utilizes the hardware monitors and operates with both hardware and software adaptation.

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Overcoming Early-Life Failure and Aging for Robust Systems

Cited by 61 publications

References 11 publications

Self-Tuning for Maximized Lifetime Energy-Efficiency in the Presence of Circuit Aging

Self-Tuning for Maximized Lifetime Energy-Efficiency in the Presence of Circuit Aging

A transient pulse dually filterable and online self-recoverable latch

Accurate and inexpensive performance monitoring for variability-aware systems

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