Overcoming the Transimpedance Limit: A Tutorial on Design of Low-Noise TIA

Abstract

Noise is probably the single most important performance metric of the high-speed transimpedance amplifier (TIA), which directly sets the sensitivity of optical receiver. The transimpedance limit which dictates the maximum achievable transimpedance gain of the TIA also turns out to fundamentally limit the TIA noise performance. In this tutorial, we analyze and explore the circuit design approaches to overcome the transimpedance limit, the key to achieve low noise, with design examples, consideration and guidelines. Both approaches can overcome the transimpedance limit, forming an effective toolkit on the design of lownoise high-speed TIA for high-sensitive CMOS optical receiver in current and future applications.

A 12.5 Gb/s 1.38 mW all-inverter-based optical receiver with multi-stage feedback TIA and continuous-time linear equalizer

“…to even lower than (4), generating higher input-referred noise [8]. Potential of high ω T is completely wasted in this scenario.…”

“…TIAs with multi-stage amplifiers are another way to extend the tranimpedance limit by achieving a higher gain-bandwidth product [3]. Unfortunately, typical multi-stage broadband amplifiers with several roughly equal non-dominant poles require significantly faster technologies to ensure that the overall phase shift in the TIA feedback loop is small enough to achieve good stability [8], which is difficult in high-speed designs. It is possible to add on-chip peaking inductors to allow for bandwidth extension in these multistage amplifier TIAs [9].…”

A 112-Gb/s —8.2-dBm Sensitivity 4-PAM Linear TIA in 16-nm CMOS With Co-Packaged Photodiodes

“…The first TIS stage having an inverter-based single-stage core amplifier with a fixed voltage supply (constrained by CMOS process) exhibits nearly the second-order system and offers slower roll-off [66]. This makes the design of following CTLEs much easier to recover the desired BW.…”

“…Note that a single-stage core amplifier with a shunt-feedback architecture is chosen for a low-noise design instead of a multi-stage core amplifier with a shunt-feedback architecture implemented in [34] and [67]. This is because the latter approach is only efficient when the ratio of f T to the desired TIA BW is much higher (i.e., >10), which cannot be satisfied in this case [66]. The latter approach also entails significant design effort overhead associated with meeting sufficient phase margin while dealing with multiple complex poles [66], [68].…”

“…This is because the latter approach is only efficient when the ratio of f T to the desired TIA BW is much higher (i.e., >10), which cannot be satisfied in this case [66]. The latter approach also entails significant design effort overhead associated with meeting sufficient phase margin while dealing with multiple complex poles [66], [68]. The noise reduction insight with considered approach can be explained as follows.…”