Overlay Control Requirements for Immersion Lithography

Abstract

Immersion lithography has been developed to meet the requirements of shrinking design rules. With it are new sources of variability and challenges which need to be understood and characterized in order to gain the most from the innovative lithography technique. This paper will focus on the immersion overlay challenges by providing a comprehensive source of variance (SOV) study of 193 immersion scanners.We will compare scenarios of 'single machine' and 'single generation matching' using wafers processed through 193nm immersion lithography tools. An ultradense sampling strategy is used to provide the data necessary to extract accurate conclusions regarding field and wafer (also referred to as "grid"), information. These measurements are then processed to determine the overlay SOV. The SOV analysis is broken down into wafer, field, and un-modeled components. A variety of overlay models and sampling schemes are then presented to illustrate how one can optimize the overlay control strategy to yield the required overlay residuals while providing the measurement robustness and throughput necessary for a high volume manufacturing environment.Finally conclusions will be drawn about optimal overlay sampling requirements and opportunities for high order correctable control (also referred to as HO or HOC).

28nm Overlay Control Improvement By Wafer Quality Enhancement and Mask Registration Control

“…If data are fit by proper model, overlay error source could be identified by coefficient of the relevant terms. The following is a typical set of high order terms: X, Y are grid coordinates, x, are field coordinates 3 .…”

“…5 is the old baseline overlay performance with residual target normalized to 1.0, and it's not enough for our requirement. When we use our data to fit [3] and [4], we find the error is focused on k12, which is Y trapezoid based on ASML intra HO instruction material. The field map illustration is shown in Fig.…”