Overlay degradation induced by film stress

Huang, Chi‐Hsiang; Liu, Yulin; Luo, Shing-Ann; Yang, Mars; Yang, Elvis; Hung, Yung-Tai; Luoh, Tuung; Yang, Tahone; Chen, K. C.

doi:10.1117/12.2256626

Cited by 4 publications

(4 citation statements)

References 3 publications

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“…When 1200 nm of silicon oxide of these two kinds was deposited on independent silicon wafer, it can be observed that the change caused by PE TEOS to the wafer curvature was 54 µm, while that caused by HDP oxide to the wafer curvature was 137 µm. In 3D NAND, big wafer bow should be avoided as it will lead to a series of problems and reduce the yield [13][14][15]. Therefore, PE TEOS is more favorable than HDP oxide when applied as PMD oxide in 3D NAND.…”

Section: The Stress Of Pe Teos and Hdp Oxidementioning

confidence: 99%

“…In order to facilitate the evolution to higher density and lower cost of flash memory, a significant step is underway: replacement of 2D NAND with 3D NAND [1][2][3][4][5][6]. As introduced, 3D NAND raises a lot of new issues regarding their fabrication, such as the multi-layer thickness [7], staircase formation [8,9], ultra-high aspect ratio channel hole etch [10][11][12], stress [13][14][15], process detection [16,17] et al In this paper, the * Authors to whom any correspondence should be addressed. challenges of pre-metal dielectric (PMD) oxide in 3D NAND are discussed.…”

Section: Introductionmentioning

confidence: 99%

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Pre-metal dielectric PE TEOS oxide pitting in 3D NAND: mechanism and solutions

Hong¹,

Xu²,

Hou³

et al. 2021

Semicond. Sci. Technol.

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In 3D NAND, as the stack number increases, the process cost becomes higher and higher, and the stress problem becomes more and more serious. Therefore, the low cost and low stress plasma enhanced Tetraethyl orthosilicate (PE TEOS), compared to high density plasma (HDP) oxide, shows its superiority as pre-metal dielectric (PMD) oxide layer in 3D NAND. This paper explores the challenges in the application of PE TEOS in 3D NAND PMD oxide layer.In our experiments, both PE TEOS and HDP are employed as the PMD oxide for 3D NAND staircase protection. There is not any void found in the two oxide structures. However, oxide pitting is spotted in the subsequent diluted hydrofluoric acid wet etching in the PE TEOS split. Moreover, we observe that the top silicon nitride corrodes in hot phosphoric acid. We investigate the mechanism of PE TEOS oxide pitting and silicon nitride corroding, and propose two solutions: 1) HDP oxide + PE TEOS, and 2) PE TEOS + dry etching.Experimental results demonstrate that our solutions can well address the issue of PE TEOS oxide pitting and effectively protect the staircase structure. This work extends the application of PE TEOS oxide of which the cost and the stress are both low in 3D NAND.

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Section: The Stress Of Pe Teos and Hdp Oxidementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Pre-metal dielectric PE TEOS oxide pitting in 3D NAND: mechanism and solutions

Hong¹,

Xu²,

Hou³

et al. 2021

Semicond. Sci. Technol.

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show abstract

“…The FG NAND stores electrons in floating gate, and each program/erase operation consumes electrons, as the cell size decreases, the number of electrons stored in the floating gate is gradually reduced, then the memory lifetime is also reduced. However, the CT NAND stores electrons in the trap layer, the number of electrons is almost unchanged, the reliability and retention are better compared with FG NAND [4][5][6][7]. Therefore, CT NAND currently has become mainstream memory.…”

Section: Introductionmentioning

confidence: 99%

A novel solution to improve saddle-shape warpage in 3D NAND flash memory

Shi¹,

Xia²,

Hu³

et al. 2020

Semicond. Sci. Technol.

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It is difficult to adjust asymmetrically saddle-shape wafer warpage resulted from high-stress material in 3D NAND Flash memory. This paper proposes a novel method that the suitable trenches on the backside of wafer is formed to improve saddle-shape warpage asymmetrically. Effects of different trench pitches, CDs and depths are studied by FEM (finite element method) simulation. This solution provides an instruction for solving warpage in 3D NAND flash memory manufacturing.

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“…1 Many generations of 3D NAND products have been successfully developed. [2][3][4][5][6] However, with the increase of the stack layers, the fabrication of 3D NAND becomes more and more challenging, such as the multi-layer thickness, 7 staircase, 8 ultra-high aspect ratio channel hole etch, 9-12 stress [13][14][15] and process detection. 16,17 This article mainly focuses on staircase.…”

mentioning

confidence: 99%

A High Density and Low Cost Staircase Scheme for 3D NAND Flash Memory: SDS(Stair Divided Scheme)

Hong

Xia

et al. 2019

ECS J. Solid State Sci. Technol.

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We propose and implement Stair Divided Scheme (SDS), a novel high density and low cost staircase scheme for 3D NAND. In SDS, the stairs are divided into m zones in Y direction, and thus only N/m stairs are needed in X direction for N control gates. We further present the photoresist (PR) consume model. The PR consume model fits the result well. Based on the PR consume model, we are able to prove the process efficiency and low cost of SDS. We also show that SDS can improve the integration for higher bit density. Finally, we find that the critical dimension (CD) of stair divided zone shifts post stair etching. We investigate the reason and point out that, it is necessary to make compensation in layout to ensure the precise alignment of stairs.

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Overlay degradation induced by film stress

Cited by 4 publications

References 3 publications

Pre-metal dielectric PE TEOS oxide pitting in 3D NAND: mechanism and solutions

Pre-metal dielectric PE TEOS oxide pitting in 3D NAND: mechanism and solutions

A novel solution to improve saddle-shape warpage in 3D NAND flash memory

A High Density and Low Cost Staircase Scheme for 3D NAND Flash Memory: SDS(Stair Divided Scheme)

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