Overlay metrology for double patterning processes

Leray, Philippe; Cheng, Stone; Laidler, David; Kandel, Daniel; Adel, Mike; Dinu, Berta; Polli, Marco; Vasconi, Mauro; Salski, Bartłomiej

doi:10.1117/12.814182

Cited by 3 publications

(6 citation statements)

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“…The study showed that the DBO can give good measurement with low contrast mark, because the measurement signal is generated by light diffraction with the overlay mark. [3] However, the DBO measurement also has its limits and is not widely used. In order to adopt the HM1 only LELE process, we need make a more precise APC control.…”

Section: Discussionmentioning

confidence: 99%

Double Patterning Lithography Alignment and OVL-Control Strategy for 20nm Technology

Yue¹,

Hao²,

Jiang³

et al. 2014

ECS Trans.

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Double patterning using 193 nm immersion lithography has been adapted as the solution to enable 20 nm technology nodes. In the Back end, Litho Etch Litho Etch (LELE) is considered as the most suitable process for this technology. The overlay control is one of the key figures for the successful realization of this technology. This paper presents a method called indirect alignment and indirect overlay measurement comparing with the common method (so called direct alignment and overlay the overlay (OVL) measurement) based on process complexity. While doing LELE, the common method need two or more films to get enough signal intensity for alignment measurement while the present method need only one film. In this paper, we will compare with the two overlay control methods and we also evaluate the risks for the present method and try to design a new APC control system to reduce the risks.

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Section: Discussionmentioning

confidence: 99%

Double Patterning Lithography Alignment and OVL-Control Strategy for 20nm Technology

Yue¹,

Hao²,

Jiang³

et al. 2014

ECS Trans.

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“…Studies suggest that IBO is better for non-tool-induced shift, while DBO is better for tool-induced shift [158,159]. However, IBO has faced more contrasting challenges when SADP and SAQP patterning film stacks have been introduced, while DBO has shown less film stack dependence with good overlay precision [160].…”

Section: Overlay and Edge Placement Error (Epe) Challengesmentioning

confidence: 99%

“…II. Fine-tuning is carried out for matching by using higher-order corrections per field on the EUV scanner [160].…”

Section: Overlay and Edge Placement Error (Epe) Challengesmentioning

confidence: 99%

“…In a multi-patterning scheme, such as SAmP and LELE, a new parameter, EPE (edge placement error) is introduced. It combines CD, overlay errors, and includes local variations of CD and LWR (line width roughness) [160]. EPE is defined as the displacement of edges of two features from their target locations, as shown in Figure 14.…”

Section: Overlay and Edge Placement Error (Epe) Challengesmentioning

confidence: 99%

“…This results in the overlap distance in both x and y direction are out of design distance, as shown in Figure 14. EPE can be calculated by an analytical method, as follows [160]:…”

Section: Overlay and Edge Placement Error (Epe) Challengesmentioning

confidence: 99%

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CMOS Scaling for the 5 nm Node and Beyond: Device, Process and Technology

Radamson,

Miao,

Zhou

et al. 2024

Nanomaterials

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After more than five decades, Moore’s Law for transistors is approaching the end of the international technology roadmap of semiconductors (ITRS). The fate of complementary metal oxide semiconductor (CMOS) architecture has become increasingly unknown. In this era, 3D transistors in the form of gate-all-around (GAA) transistors are being considered as an excellent solution to scaling down beyond the 5 nm technology node, which solves the difficulties of carrier transport in the channel region which are mainly rooted in short channel effects (SCEs). In parallel to Moore, during the last two decades, transistors with a fully depleted SOI (FDSOI) design have also been processed for low-power electronics. Among all the possible designs, there are also tunneling field-effect transistors (TFETs), which offer very low power consumption and decent electrical characteristics. This review article presents new transistor designs, along with the integration of electronics and photonics, simulation methods, and continuation of CMOS process technology to the 5 nm technology node and beyond. The content highlights the innovative methods, challenges, and difficulties in device processing and design, as well as how to apply suitable metrology techniques as a tool to find out the imperfections and lattice distortions, strain status, and composition in the device structures.

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