Oversampling A-to-D and D-to-A converters with multistage noise shaping modulators

Uchimura, K.; Hayashi, Toshiyuki; Kimura, T.; Iwata, Atsushi

doi:10.1109/29.9034

Cited by 114 publications

(21 citation statements)

References 13 publications

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“…As is well known in the art, for an th-order MASH modulator the only noise term that appears in the output is the binary quantizer error from the last stage [1], [19]. The reason for this is that, as mentioned before, the quantizer error from all stages except the last one is cancelled in the error cancellation network.…”

Section: B Higher Order Mash Modulatormentioning

confidence: 94%

“…The input to the modulator goes into the first stage, and the negative of the binary quantizer error sequence from the first stage is fed forward into the second stage as its input, and visa versa. The outputs from all stages are processed by an error cancellation network, which removes the binary quantizer error components from all the stages except the last one [1], [2], and [19]. The difference equations describing the th-order MASH modulator are given as follows:…”

Section: B Higher Order Mash Modulatormentioning

confidence: 99%

“…Exact analysis of the first-order modulator with dc inputs was performed by Gray in [18], where it was shown that the output spectrum consists of discrete spectral spikes whose locations and amplitudes are input value dependent. The technique was then extended for the higher order multistage noise shaping (MASH) [19] modulators in [20] and [21], using concepts from ergodic theory. All of these exact analysis studies were based on obtaining a nonlinear difference equation from which the asymptotic autocorrelation function of the binary quantizer error was determined.…”

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confidence: 99%

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Rigorous Analysis of Delta–Sigma Modulators for Fractional-<tex>$N$</tex>PLL Frequency Synthesis

Kozak

Kale

2004

IEEE Trans. Circuits Syst. I

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Abstract-In this paper, rigorous analyses are presented for higher order multistage noise shaping (MASH) Delta-Sigma (16) modulators, which are built out of cascaded first-order stages, with rational dc inputs and nonzero initial conditions. Asymptotic statistics such as the mean, average power, and autocorrelation of the binary quantizer error are formulated using a nonlinear difference equation approach. An important topic of interest considered here is the fractional-phase-locked-loop frequency synthesis applications, where the input to the modulator has to be a rational constant. It has been mathematically shown that, regardless of the initial conditions, first-order and second-order MASH 16 modulators with rational dc inputs cannot sufficiently randomize the quantization error samples, and, therefore, are not suitable for fractionalsynthesis applications. An irrational initial condition imposed on the first accumulator of a third or higher order MASH modulator, on the other hand, annihilates the tones throughout the whole output spectrum, and provides a very smooth noise shaping. Simulation results are provided to support the theoretically derived results. Implementation issues of the irrational initial condition in the digital domain are also discussed and investigated together with the effect of finite accumulator size on the noise-shaping quality factor.

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Section: B Higher Order Mash Modulatormentioning

confidence: 94%

Section: B Higher Order Mash Modulatormentioning

confidence: 99%

mentioning

confidence: 99%

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Rigorous Analysis of Delta–Sigma Modulators for Fractional-<tex>$N$</tex>PLL Frequency Synthesis

Kozak

Kale

2004

IEEE Trans. Circuits Syst. I

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“…2(a). This is functionally equivalent to a MASH cascade of first-order, single-bit delta-sigma modulators [40], where the quantization "noise" of the integrator of one stage feeds into the next [37], [38]. To visualize this equivalence, notice that the integration loop ("sigma") and the quantization residue ("delta") operations in Fig.…”

Section: B Cascade and Cellular Stucturesmentioning

confidence: 99%

Delta-sigma cellular automata for analog VLSI random vector generation

Cauwenberghs

1999

IEEE Trans. Circuits Syst. II

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Abstract-We present a class of analog cellular automata for parallel analog random vector generation, including theory on the randomness properties, scalable parallel very large scale integration (VLSI) architectures, and experimental results from an analog VLSI prototype with 64 channels. Linear congruential coupling between cells produces parallel channels of uniformly distributed random analog values, with statistics that are uncorrelated both across channels and over time.

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“…Besides modeling capacitive mismatch , the gain parameters may serve the purpose of improving the stability of noise shaping and increasing the input dynamic range in the standard second-order modulator [16] with single-bit feedback, for a nominal gain less than one ( ) [17]. From (2) in the -domain, either modulator satisfies the linear FIR recurrence relation (4) or, equivalently, in terms of the quantization error (residue) (5) where, for the first-order modulator ( ) (6) and for the second-order modulator ( ) …”

Section: B Linear Error Model Of Modulator Structuresmentioning

confidence: 99%

Adaptive digital correction of analog errors in MASH ADCs. I. Off-line and blind on-line calibration

Cauwenberghs

Temes

2000

IEEE Trans. Circuits Syst. II

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Abstract-Cascaded delta-sigma (MASH) modulators for higher order oversampled analog-to-digital conversion rely on precise matching of contributions from different quantizers to cancel lower order quantization noise from intermediate delta-sigma stages. This first part of the paper studies the effect of analog imperfections in the implementation, such as finite gain of the amplifiers and capacitor ratio mismatch, and presents algorithms and architectures for digital correction of such analog imperfections, as well as gain and spectral distortion in the signal transfer function. Digital correction is implemented by linear finite-impulse response (FIR) filters, of which the coefficients are determined through adaptive off-line or on-line calibration. Of particular interest is an on-line "blind" calibration technique, that uses no reference and operates directly on the digital output during conversion, with the only requirement on the unknown input signal that its spectrum be bandlimited. Behavioral simulations on dual-quantization oversampled converters demonstrate near-perfect adaptive correction and significant improvements in signal-to-quantization-noise performance over the uncalibrated case, using as few as 5 FIR coefficients. An alternative on-line adaptation technique using test signal injection and experimental results from silicon are presented in the second part, in a companion paper [1].

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Oversampling A-to-D and D-to-A converters with multistage noise shaping modulators

Cited by 114 publications

References 13 publications

Rigorous Analysis of Delta–Sigma Modulators for Fractional-<tex>$N$</tex>PLL Frequency Synthesis

Rigorous Analysis of Delta–Sigma Modulators for Fractional-<tex>$N$</tex>PLL Frequency Synthesis

Delta-sigma cellular automata for analog VLSI random vector generation

Adaptive digital correction of analog errors in MASH ADCs. I. Off-line and blind on-line calibration

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Oversampling A-to-D and D-to-A converters with multistage noise shaping modulators

Cited by 114 publications

References 13 publications

Rigorous Analysis of Delta–Sigma Modulators for Fractional-&lt;tex&gt;$N$&lt;/tex&gt;PLL Frequency Synthesis

Rigorous Analysis of Delta–Sigma Modulators for Fractional-&lt;tex&gt;$N$&lt;/tex&gt;PLL Frequency Synthesis

Delta-sigma cellular automata for analog VLSI random vector generation

Adaptive digital correction of analog errors in MASH ADCs. I. Off-line and blind on-line calibration

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Rigorous Analysis of Delta–Sigma Modulators for Fractional-<tex>$N$</tex>PLL Frequency Synthesis

Rigorous Analysis of Delta–Sigma Modulators for Fractional-<tex>$N$</tex>PLL Frequency Synthesis