Overview of a Software Defined Downlink Inner Receiver for Category-E LTE-Advanced UE

Li, Min; Appeltans, Raf; Amin, Amir; Torrea-Duran, Rodolfo; Cappelle, Hans; Hartmann, Matthias; Yomo, Hidekuni; Kobayashi, Kenzo; Dejonghe, Antoine; Perre, Liesbet Van der

doi:10.1109/icc.2011.5963387

Cited by 10 publications

(8 citation statements)

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“…Thus it is possible to compile/map C source code for the ADRES processor using the DRESC tool chain. In this paper, the high throughput baseband ADRES instance [1] is chosen as the platform. It employs a 256-bit wide data path, which is able to process 8 complex values in parallel in wireless applications.…”

Section: The Sdr Baseband Processor and Adres Architecturementioning

confidence: 99%

“…The SandBridge [11] technologies design multi-core multi-thread architectures using Sandblaster DSP cores. The ADRES architecture proposed in [1] is a baseband processor which employs several 256-bit FUs to meet the real-time requirements of wireless protocols. With the assistance of tool-chains, the parameterizable ADRES is a good platform to carry out design exploration.…”

Section: Related Workmentioning

confidence: 99%

“…ADRES is the abbreviation for Architecture for Dynamically Reconfigurable Embedded Systems. It is a reconfigurable template [1], [19] which can meet real-time throughput requirements of the state-of-the-art wireless standards/protocols like 802.11n/ad and 3GPP LTE. This architecture supports C language software development with the Dynamically Reconfigurable Embedded Systems Compiler (DRESC) tool chain.…”

Section: The Sdr Baseband Processor and Adres Architecturementioning

confidence: 99%

“…Software Defined Radio (SDR) is an approach to implement the baseband algorithms primarily in software, which demands parallel processing power to meet power and processing requirements. Recently, several baseband processors, such as ADRES [1], AnySP [2], EVP [3], have been developed to meet these programmability, performance, and power consumption requirements.…”

Section: Introductionmentioning

confidence: 99%

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Exploration of Full HD Media Decoding on a Software Defined Radio Baseband Processor

Chen

Cao

et al. 2013

IEEE Trans. Signal Process.

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Recently, various specialized Software Defined Radio (SDR) baseband processors have been proposed for meeting the high performance and programmability requirements for emerging wireless communication applications. In order to support high throughput wireless communication, the SDR baseband processors typically employ many parallel computation elements, which may also be used for performing other signal processing applications. This paper explores the feasibility of performing complex media processing on such SDR baseband processors. Specifically, the full HD 1080p state-of-the-art H.264/AVC media decoding has been implemented onto a recent version of the ADRES based SDR baseband processor. Since the processor was originally designed exclusively for wireless baseband applications, algorithm and architecture co-optimizations are required to make the goal feasible. Following algorithm analysis, the computationally dominant tasks of the H.264/AVC, including the motion compensation, the intra prediction, the inverse integer transform, and the deblocking filter, have been selected to be mapped onto the ADRES. The experimental results show that, with limited architectural extensions, the ADRES based baseband processor achieves competitive performance efficiency, even compared with several processors that are specifically optimized for the media decoding application.Index Terms-Baseband processor, H.264/AVC decoder, full HD, SIMD.

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Section: The Sdr Baseband Processor and Adres Architecturementioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: The Sdr Baseband Processor and Adres Architecturementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Exploration of Full HD Media Decoding on a Software Defined Radio Baseband Processor

Chen

Cao

et al. 2013

IEEE Trans. Signal Process.

Self Cite

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“…Besides the disadvantages of [5], these schemes have much larger feedback latency. Because the throughput and complexity are key criteria for SDR [11,12], the above schemes are not suitable for SDR implementation.…”

Section: Introductionmentioning

confidence: 99%

LTE uplink MIMO receiver with low complexity interference cancellation

Yin

Cavallaro

2012

Analog Integr Circ Sig Process

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In LTE/LTE-A uplink receiver, frequency domain equalizers (FDE) are adopted to achieve good performance. However, in multi-tap channels, the residual inter-symbol and inter-antenna interference still exist after FDE and degrade the performance. Conventional interference cancellation schemes can minimize this interference by using frequency domain interference cancellation. However, those schemes have high complexity and large feedback latency, especially when adopting a large number of iterations. These result in low throughput and require a large amount of resource in software defined radio implementation. In this paper, we propose a novel low complexity interference cancellation scheme to minimize the residual interference in LTE/LTE-A uplink. Our proposed scheme can bring about 2 dB gains in different channels, but only adds up to 7.2 % complexity to the receiver. The scheme is further implemented on Xilinx FPGA. Compared to other conventional interference cancellation schemes, our scheme has less complexity, less data to store, and shorter feedback latency.

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