Overview of Signal Integrity and EMC Design Technologies on PCB: Fundamentals and Latest Progress

Wu, Tzong–Lin; Buesink, Frits; Canavero, Flavio

doi:10.1109/temc.2013.2257796

Cited by 185 publications

(13 citation statements)

References 114 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Evaluation of signal integrity.-For the interpretation of SI analysis in the time-domain of on-chip interconnects, the characteristic of interconnects are extracted through eye diagram metrics (eye height and eye width) 40 in a channel simulator (CS). The CS performs simulations using circuit-level and it can be verified.…”

Section: Resultsmentioning

confidence: 99%

Evaluation and Reduction of Signal Integrity Issues in Multiwalled Carbon Nanotube On-Chip VLSI Interconnects

Mudavath¹,

Naik²,

Jeripotula³

2021

ECS J. Solid State Sci. Technol.

View full text Add to dashboard Cite

Due to advancements in device scaling in very-large-scale integration (VLSI) technology, signal integrity (SI) issues play a major role to determining the performance of on-chip interconnects in high-speed digital circuits. The main SI issues are delays, peak voltage noise effects, crosstalk, and timing uncertainties. Here, the SI issues of the coupled multi-walled carbon nanotube (MWCNT) on-chip interconnects are evaluated with and without the effect of shielding technique and compared to the copper interconnects. The MWCNT exhibits an average of 47.9% smaller propagation delays than Cu in dynamic crosstalk conditions. Further, for crosstalk reduction, the active shielding (AS) and passive shielding (PS) techniques are proposed. With the AS and PS techniques, the MWCNT interconnects experience a decreased delay by 46.8% and 30.15% compared to without shielding technique, respectively. Moreover, the AS exhibits smaller crosstalk effects than the PS technique due to its input switching activities on shielded lines. In addition, the quality of the signal (QoS) and Intersymbol interference (ISI) noise effects of coupled MWCNT interconnect with and without shielding is evaluated. Finally, to improve the QoS and reduce the ISI effects, the decision feedback equalizer with the least mean square adaptive algorithm is implemented at the receiver end.

show abstract

Section: Resultsmentioning

confidence: 99%

Evaluation and Reduction of Signal Integrity Issues in Multiwalled Carbon Nanotube On-Chip VLSI Interconnects

Mudavath¹,

Naik²,

Jeripotula³

2021

ECS J. Solid State Sci. Technol.

View full text Add to dashboard Cite

show abstract

“…This time-variant current, however, generally exists in one of the two possible forms: magnetic current elements in the magnetic field sources and electric dipoles in the electric field sources (Kim and Li 2010; Wu et al 2013). Based on this description above, the electric dipole and magnetic dipole can be selected to replace the magnetic field and electric field of the time varying current in the integrated circuit.…”

Section: Electro-magnetic Model Based On Dipolementioning

confidence: 99%

Electro-magnetic analysis of high-frequency digital signal processors

Lei

Meiyuan

et al. 2016

SpringerPlus

View full text Add to dashboard Cite

High-frequency digital signal processors are increasingly suffering from electro-magnetic interference, due to its ever-increasing integration level and operation speed. The accurate prediction of its electro-magnetic effects require less effort to be spared in the design procedures to obtain better electro-magnetic compatibility and to avoid later modifications that are lengthy and expensive. In this paper, the dipole method is implemented to predict the magnetic impacts of DSP6713 system in order to reduce its design costs.

show abstract

“…The performance of filter is not only influenced by schematic design, but also by PCB layout [9]. However, it has never been taken into consideration in the calculation process, which is the reason why the real EFT test is needed for confirmation.…”

Section: Comparison By Real Testmentioning

confidence: 99%

The optimization of electrical fast transient filter

Xin-wu

Lin

2014

IEICE Electron. Express

View full text Add to dashboard Cite

In order to solve the problem that power supply of the sensor in a certain type of acceleration monitor fails under the 2 kV level of EFT test, this article aims to design an optimized EFT filter based on the current typical one. In fact, the insertion loss and output voltage are both calculated by equivalent circuit. According to the comparison between the new filter and the typical one, it can be concluded that the optimized filter tends to function with better performances and efficiency, which can be confirmed by the EFT test.

show abstract

Overview of Signal Integrity and EMC Design Technologies on PCB: Fundamentals and Latest Progress

Cited by 185 publications

References 114 publications

Evaluation and Reduction of Signal Integrity Issues in Multiwalled Carbon Nanotube On-Chip VLSI Interconnects

Evaluation and Reduction of Signal Integrity Issues in Multiwalled Carbon Nanotube On-Chip VLSI Interconnects

Electro-magnetic analysis of high-frequency digital signal processors

The optimization of electrical fast transient filter

Contact Info

Product

Resources

About