Overview of the FREEDOM Compiler for Mapping DSP Software to FPGAs

Zaretsky, David; Mittal, Mayank; Tang, Xiaoyong; Banerjee, P.

doi:10.1109/fccm.2004.44

Cited by 15 publications

(10 citation statements)

References 23 publications

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“…The CDFGs were generated from assembly code using the FREEDOM compiler [9][10], and were unrolled several times, thereby increasing design complexity. Table 1 shows results for varying look-ahead and backtracking depths in terms of the number of templates generated, the maximum template size, the percentage resources reduced, and the total run time for the resource sharing.…”

Section: Resultsmentioning

confidence: 99%

“…The contribution of this work is an area optimization algorithm that uses regularity extraction to generate templates of reoccurring patterns for resource sharing. This work was motivated by our experience with the FREEDOM compiler [9][10], which translates software binaries into hardware descriptions for FPGAs. The proposed approach is related to the technology mapping and the graph covering problems.…”

Section: Introductionmentioning

confidence: 99%

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Dynamic template generation for resource sharing in control and data flow graphs

Zaretsky

Mittal

Dick

et al. 2006

19th International Conference on VLSI Design Held Jointly With 5th International Conference on Embedded Systems Design (VLSID'0

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Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Dynamic template generation for resource sharing in control and data flow graphs

Zaretsky

Mittal

Dick

et al. 2006

19th International Conference on VLSI Design Held Jointly With 5th International Conference on Embedded Systems Design (VLSID'0

Self Cite

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“…This methodology was incorporated in the FREEDOM compiler, which translates DSP assembly code into hardware descriptions for FPGAs. The techniques described in this paper were briefly discussed in previous work [11,19]; here we present a more refined and elegant approach in greater detail.…”

Section: Introductionmentioning

confidence: 99%

“…The correctness of the methodology presented in this paper was verified using the FREEDOM compiler [11,19] on 8 highly pipelined benchmarks in the Texas Instruments C6000 DSP assembly language. The FREEDOM compiler generated CDFGs and RTL code targeting the Xilinx Virtex II FPGA.…”

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confidence: 99%

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Generation of Control and Data Flow Graphs from Scheduled and Pipelined Assembly Code

Zaretsky

Mittal

Dick

et al. 2006

Languages and Compilers for Parallel Computing

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Abstract. High-level synthesis tools generally convert abstract designs described in a high-level language into a control and data flow graph (CDFG), which is then optimized and mapped to hardware. However, there has been little work on generating CDFGs from highly pipelined software binaries, which complicate the problem of determining data flow propagation and dependencies. This paper presents a methodology for generating CDFGs from highly pipelined and scheduled assembly code that correctly represents the data dependencies and propagation of data through the program control flow. This process consists of three stages: generating a control flow graph, linearizing the assembly code, and generating the data flow graph. The proposed methodology was implemented in the FREEDOM compiler and tested on 8 highly pipelined software binaries. Results indicate that data dependencies were correctly identified in the designs, allowing the compiler to perform complex optimizations to reduce clock cycles.

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Combining static and dynamic array detection for binary synthesis with multiple memory ports

Rotem

Asher

2010

Des Autom Embed Syst

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In High-Level Synthesis, Binary Synthesis is a method for synthesizing compiled applications for which the source code is not available. One of the advantages of FPGAs over processors is the availability of multiple internal and external memory banks. Binary synthesis tools use multiple memory banks if they are able to recover data-structures from the binary. In this work we improve the recovery of data-structures by introducing dynamic memory analysis and combining it with improved static memory analysis. We show that many applications can only be synthesized using dynamic memory analysis. We present two FPGA based architectures for implementing the bound-checking and recovery for the synthesized code. Our experiments show that the proposed technique accelerates the execution of applications which use multiple memory banks concurrently. We demonstrate that many binary applications indeed benefit from this technique.

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Overview of the FREEDOM Compiler for Mapping DSP Software to FPGAs

Abstract: Applications that require digital signal processing (DSP)

Cited by 15 publications

References 23 publications

Dynamic template generation for resource sharing in control and data flow graphs

Dynamic template generation for resource sharing in control and data flow graphs

Generation of Control and Data Flow Graphs from Scheduled and Pipelined Assembly Code

Combining static and dynamic array detection for binary synthesis with multiple memory ports

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