Oxide Liner, Barrier and Seed Layers, and Cu-Plating of Blind Through Silicon Vias (TSVs) on 300mm Wafers for 3D IC Integration

Abstract

In this study, key enabling technologies such as the oxide liner by the PECVD, the barrier and seed layers by the PVD, and Cu-plating of blind TSVs on 300mm wafers for 3D integration are investigated. Emphases are placed on the determination and optimization of the important parameters for each of the key enabling technologies. Also, leakage currents of the fabricated Cu-filled TSVs are measured. Furthermore cross sections and SEM of the fabricated TSVs are provided and examined.

Supply chains for 3D IC integration manufacturing

“…Figure 2 shows the critical steps and ownerships. After FEOL (to pattern the devices) and MOL (to make the metal contacts) of the CPU or SoC wafer, the TSVs are fabricated by 5 key steps, namely via formation by deep reactive ion etch, for example [10], dielectric deposition by plasma enhance chemical vapor deposition, barrier and seed layer by physical vapor deposition, Cu-filling by electroplating, for example [11], and chemical-mechanical polishing to remove the overburden Cu, for example [12]. Then build up the metal layers and finally the passivation/openings (BEOL).…”

Recent Advances and New Trends in Nanotechnology and 3D Integration for Semiconductor Industry

“…This test vehicle can be degenerated to the case of: (a) wide I/O memory if there is not the memory-chip stacking nor the TSVs in the mechanical/thermal chips and the interposer is either an logic, microprocessor, or SoC; (b) wide I/O DRAM if there are not mechanical and thermal chips and the interposer is a logic chip; and (c) wide I/O interface if there is not the memory-chip stacking and there is not any TSV in the thermal/ mechanical chips. Thus, the core enabling technologies (such as via etching, dielectric, barrier and seed layers deposition, via filling, CMP, thin-wafer handling, electrical and thermal design and test of TSVs, wafer bumping of ultra finepitch lead-free microbumps, fluxless C2W bonding, electronmigration of microbumps, and reliability of microbump assemblies) developed [19][20][21][22][23][24][25][26][27][28][29][30][31][32][33][34][35][36] with this test vehicle are very useful and can have very broad applications. surrounding Si as shown in Figure 9.…”