Oxide Wearout, Breakdown, and Reliability

Dumin, D.J.

doi:10.1016/s0129-1564(01)00098-8

Cited by 11 publications

(2 citation statements)

References 349 publications

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“…There is strong empirical evidence, see, for example, Dumin [4], that suggests the time until dielectric breakdown of a thin oxide follows an extreme value distribution. Suñé et al [13] suggest that the time until breakdown follows a gamma distribution, while Sahimi [12] provides reasons for time until breakdown to follow an extreme value distribution.…”

Section: Introductionmentioning

confidence: 99%

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An Analytical Approach for the Breakdown Distribution of a Thin Oxide

Kiessler

Nimitkiatklai

2020

Prob. Eng. Inf. Sci.

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Dielectric breakdown in a thin oxide is presented in terms of an interacting particle system on a two-dimensional lattice. All edges in the system are initially assumed to be closed. An edge between two adjacent vertices will open according to an exponentially distributed random variable. Breakdown occurs at the time an open path connects the top layer of the lattice to the bottom layer. Using the extreme value theory, we show that the time until breakdown is asymptotically Weibull distributed.

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Section: Introductionmentioning

confidence: 99%

“…Our particle system models the dielectric breakdown phenomenon as presented in Degraeve et al [3] and Dumin [4]. We initially assume that the oxide is perfect containing no electron trap.…”

Section: Introductionmentioning

confidence: 99%

An Analytical Approach for the Breakdown Distribution of a Thin Oxide

Kiessler

Nimitkiatklai

2020

Prob. Eng. Inf. Sci.

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Analog switch device using a MOS structure

Juárez

Díaz

Pacio

et al. 2008

Microelectronics Journal

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Impact of single pMOSFET dielectric degradation on NAND circuit performance

Estrada

Ogas

Southwick

et al. 2008

Microelectronics Reliability

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Degradation of CMOS NAND logic circuits resulting from dielectric degradation of a single pMOSFET using constant voltage stress has been examined by means of a switch matrix technique. As a result, the NAND gate rise time increases by greater than 65%, which may lead to timing errors in high frequency digital circuits. In addition, the NAND gate DC switching point voltage shifts by nearly 11% which may be of consequence for analog or mixed signal applications. Experimental results for the degraded pMOSFET reveal a decrease in drive current by approximately 43%. There is also an increase in threshold voltage by 23%, a decrease in source to drain conductance of 30%, and an increase in channel resistance of about 44%. A linear relationship between the degradation of the pMOSFET channel resistance and the increase in NAND gate rise time is demonstrated, thereby providing experimental evidence of the impact of a single degraded pMOSFET on NAND circuit performance.

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Oxide Wearout, Breakdown, and Reliability

Cited by 11 publications

References 349 publications

An Analytical Approach for the Breakdown Distribution of a Thin Oxide

An Analytical Approach for the Breakdown Distribution of a Thin Oxide

Analog switch device using a MOS structure

Impact of single pMOSFET dielectric degradation on NAND circuit performance

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