Oxide Wearout, Breakdown, and Reliability

Dumin, D.J.

doi:10.1142/9789812778062_0001

Cited by 11 publications

(5 citation statements)

References 297 publications

(425 reference statements)

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“…In this respect, we shed light in this section on the structural damage that occurs during the BD current transient. In ultra-thin dielectric layers (<5 nm), there is a wide consensus around considering that the intrinsic BD is related to the generation of defects in the dielectric film [ 163 , 164 , 165 , 166 ]. When the density of bulk defects is high enough, the BD event is triggered by the local connection of the electrodes through a defect related conduction path.…”

Section: Thermometry Of Conducting Filamentsmentioning

confidence: 99%

On the Thermal Models for Resistive Random Access Memory Circuit Simulation

et al. 2021

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Resistive Random Access Memories (RRAMs) are based on resistive switching (RS) operation and exhibit a set of technological features that make them ideal candidates for applications related to non-volatile memories, neuromorphic computing and hardware cryptography. For the full industrial development of these devices different simulation tools and compact models are needed in order to allow computer-aided design, both at the device and circuit levels. Most of the different RRAM models presented so far in the literature deal with temperature effects since the physical mechanisms behind RS are thermally activated; therefore, an exhaustive description of these effects is essential. As far as we know, no revision papers on thermal models have been published yet; and that is why we deal with this issue here. Using the heat equation as the starting point, we describe the details of its numerical solution for a conventional RRAM structure and, later on, present models of different complexity to integrate thermal effects in complete compact models that account for the kinetics of the chemical reactions behind resistive switching and the current calculation. In particular, we have accounted for different conductive filament geometries, operation regimes, filament lateral heat losses, the use of several temperatures to characterize each conductive filament, among other issues. A 3D numerical solution of the heat equation within a complete RRAM simulator was also taken into account. A general memristor model is also formulated accounting for temperature as one of the state variables to describe electron device operation. In addition, to widen the view from different perspectives, we deal with a thermal model contextualized within the quantum point contact formalism. In this manner, the temperature can be accounted for the description of quantum effects in the RRAM charge transport mechanisms. Finally, the thermometry of conducting filaments and the corresponding models considering different dielectric materials are tackled in depth.

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Section: Thermometry Of Conducting Filamentsmentioning

confidence: 99%

On the Thermal Models for Resistive Random Access Memory Circuit Simulation

et al. 2021

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“…Using the integrated coil approach, SiO 2 , the intermetal filling of the CMOS process behaves as the isolation barrier. Following the reported mean time to failure of 450 V/µm for 20 years [12], and 2 µm of spacing between process second and the top metal layer, above 900 V of isolation working voltage (V iso ) is achieved in this design. Further increase of the V iso can be obtained through a smaller process with a greater number of metal layers and consequently a thicker isolation barrier.…”

Section: Integrated Spiral Coilmentioning

confidence: 83%

A Small Footprint Digital Isolator Based on CMOS Integrated Hall-Effect Sensor

2022

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“…Texas Instrument ISO72xx [14]). Based on the oxide deterioration profile reported in [15], one micron of oxide has an isolation breakdown voltage of 0.45 MV/mm. Hence, having 2 μm of oxide, theoretical 900 V of isolation working voltage (V iso ) is expected.…”

Section: Integrated Spiral Coilsmentioning

confidence: 99%

A Fully Integrated Low-Power Hall-Based Isolation Amplifier With IMR Greater Than 120 dB

Mirfakhraei

Audet

Hassan

2022

IEEE Trans. Circuits Syst. I

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A CMOS Hall-based fully integrated isolation amplifier for differential voltage sensing is presented in this work. The design is fabricated in a 0.35 µm CMOS process in which the high voltage (HV) side of the amplifier contains a coil driver while the low voltage (LV) side includes a Hall-effect sensor, lownoise amplifier, programmable-gain amplifier, filter, and chopper switches. Another Hall sensor performs the digital isolation using the on-off keying (OOK) technique for clock recovery. The introduced prototype achieves above 120 dB of isolation mode rejection (IMR) at 60 Hz and operates at a continuous isolation working voltage of 0.6 kV. It has also a maximum nonlinearity of 0.64 %, an input-referred offset of 1 mV, a 40 dB full-scale signal-to-noise ratio over a 40 kHz bandwidth, and a spurious-free dynamic range of 64 dB. The silicon area for each of the two separate dices employed for the HV and LV side of the isolation amplifier is 1 mm 2 with a power consumption of 7.6 mW and 9.9 mW respectively. The achieved miniaturized size of the isolation components, as well as their significantly low-power consumption, ensure the suitability of the proposed isolation amplifier for multi-channel readout circuit applications.

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Oxide Wearout, Breakdown, and Reliability

Cited by 11 publications

References 297 publications

On the Thermal Models for Resistive Random Access Memory Circuit Simulation

On the Thermal Models for Resistive Random Access Memory Circuit Simulation

A Small Footprint Digital Isolator Based on CMOS Integrated Hall-Effect Sensor

A Fully Integrated Low-Power Hall-Based Isolation Amplifier With IMR Greater Than 120 dB

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