Oxygen-Dependent Instability and Annealing/Passivation Effects in Amorphous In–Ga–Zn–O Thin-Film Transistors

Chen, Wei-Tsung; Lo, Shih-Yi; Kao, Sung‐Shuo; Zan, Hsiao‐Wen; Tsai, Chuang-Chuang; Lin, Jiunn-Yuan; Fang, Chun‐Hsiung; Lee, Chung‐Chun

doi:10.1109/led.2011.2165694

Cited by 184 publications

(109 citation statements)

References 15 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Following the positive voltage stress tests, neither shifted to the left nor deteriorated. These results accord with the trend observed for Si 3 N 4 sample and the characteristics of positive gate voltage stress [19][20][21]. This phenomenon is attributed to the interface effect between the gate-insulating layer and the IGZO.…”

Section: Resultssupporting

confidence: 91%

Interface Study on Amorphous Indium Gallium Zinc Oxide Thin Film Transistors Using High‐k Gate Dielectric Materials

Lin

Chou

2015

Journal of Nanomaterials

View full text Add to dashboard Cite

We investigated amorphous indium gallium zinc oxide (a-IGZO) thin film transistors (TFTs) using different high-k gate dielectric materials such as silicon nitride (Si 3 N 4 ) and aluminum oxide (Al 2 O 3 ) at low temperature process (<300 ∘ C) and compared them with low temperature silicon dioxide (SiO 2 ). The IGZO device with high-k gate dielectric material will expect to get high gate capacitance density to induce large amount of channel carrier and generate the higher drive current. In addition, for the integrating process of integrating IGZO device, postannealing treatment is an essential process for completing the process. The chemical reaction of the high-k/IGZO interface due to heat formation in high-k/IGZO materials results in reliability issue. We also used the voltage stress for testing the reliability for the device with different high-k gate dielectric materials and explained the interface effect by charge band diagram.

show abstract

Section: Resultssupporting

confidence: 91%

Interface Study on Amorphous Indium Gallium Zinc Oxide Thin Film Transistors Using High‐k Gate Dielectric Materials

Lin

Chou

2015

Journal of Nanomaterials

View full text Add to dashboard Cite

show abstract

“…Table 1 The initial TFT properties of devices A, B, and C. minimized is effective in obtaining good electrical performances, such as high mobility and low SS in IGZO TFTs. On the other hand, it has been reported that the bottom gate TFTs fabricated in the high P O 2 is more vulnerable to the V th instability under PBS [28] due to the electron trapping by the acceptor-like states related with interstitial oxygen in the active bulk [29] or acceptor-like state generation in the upper half of the bandgap [30]. Figure 5, however, shows that device B with interfacial a-IGZO of 10 nm thickness deposited under low P O 2 , showed a dramatic improvement of V th stability under PBS compared to that of device A.…”

Section: CMmentioning

confidence: 99%

Influence of gate dielectric/channel interface engineering on the stability of amorphous indium gallium zinc oxide thin-film transistors

Cho

Ryu

Kim

et al. 2014

Phys. Status Solidi A

View full text Add to dashboard Cite

We report the simultaneous improvements of the threshold voltage (V th ) stabilities under the prolonged positive gate bias stress (PBS) and negative gate bias under illumination stress (NBIS) by employing the gate dielectric/channel interface engineering in the bottom-gate, DC-sputtered amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors (TFT). In the interfacial region, a-IGZO is grown under the low oxygen partial pressure (P O2 ) condition to minimize the damage from highly energetic oxygen anion bombardment into the substrate during sputtering. Meanwhile, high P O2 is employed during the bulk growth of active film to reduce the oxygen vacancy (V O ) related defects in a-IGZO, which is known to be a main cause for the degradation of the electrical properties of TFT under NBIS. Owing to the lower damage of the gate dielectric by interface engineering during sputter deposition, the charge trapping or injection probability into the gate dielectric is diminished. Consequently, V th instabilities due to both the electron trapping under PBS and the trapping of positively charged species under NBIS are alleviated simultaneously.

show abstract

“…Variations of dielectric gate material, use of high temperatures treatments, passivation of the channel backside lead to considerable improvement of oxide transistors stability. [1][2][3] However such solutions limit the area of their possible implementation. For example, the annealing at temperatures higher 300 C makes application of flexible (polymer) substrates impossible.…”

Section: Introductionmentioning

confidence: 99%

Effect of indium low doping in ZnO based TFTs on electrical parameters and bias stress stability

2015

View full text Add to dashboard Cite

Some applications of thin film transistors (TFTs) need the bottom-gate architecture and unpassivated channel backside. We propose a simple routine to fabricate indium doped ZnO-based TFT with satisfactory characteristics and acceptable stability against a bias stress in ambient room air. To this end, a channel layer of 15 nm in thickness was deposited on cold substrate by DC reactive magnetron co-sputtering of metal Zn-In target. It is demonstrated that the increase of In concentration in ZnO matrix up to 5% leads to negative threshold voltage (VT) shift and an increase of field effect mobility (μ) and a decrease of subthreshold swing (SS). When dopant concentration reaches the upper level of 5% the best TFT parameters are achieved such as VT = 3.6 V, μ = 15.2 cm2/V s, SS = 0.5 V/dec. The TFTs operate in enhancement mode exhibiting high turn on/turn off current ratio more than 106. It is shown that the oxidative post-fabrication annealing at 250oC in pure oxygen and next ageing in dry air for several hours provide highly stable operational characteristics under negative and positive bias stresses despite open channel backside. A possible cause of this effect is discussed.

show abstract

Oxygen-Dependent Instability and Annealing/Passivation Effects in Amorphous In–Ga–Zn–O Thin-Film Transistors

Cited by 184 publications

References 15 publications

Interface Study on Amorphous Indium Gallium Zinc Oxide Thin Film Transistors Using High‐k Gate Dielectric Materials

Interface Study on Amorphous Indium Gallium Zinc Oxide Thin Film Transistors Using High‐k Gate Dielectric Materials

Influence of gate dielectric/channel interface engineering on the stability of amorphous indium gallium zinc oxide thin-film transistors

Effect of indium low doping in ZnO based TFTs on electrical parameters and bias stress stability

Contact Info

Product

Resources

About