P 2 IP: A novel low-latency Programmable Pipeline Image Processor

Abstract

This paper presents a novel systolic Coarse-Grained Reconfigurable Architecture for real-time image and video processing called P 2 IP. The P 2 IP is a scalable architecture that combines the low-latency characteristic of systolic array architectures with a runtime reconfigurable datapath. Reconfigurability of the P 2 IP enables it to perform a wide range of image pre-processing tasks directly on a pixel stream. The versatility of the P 2 IP is demonstrated through three image processing algorithms mapped onto the architecture, implemented in an FPGA-based platform. The obtained results show that the P 2 IP can achieve up to 129 fps in Full HD 1080p and 32 fps in 4K 2160p what makes it suitable for modern high-definition applications.

A New Mapping Methodology for Coarse-Grained Programmable Systolic Architectures

“…This algorithm transforms the mapping problem into a graph minor problem between the application model and the hardware model. Possa et al [18] present a MATLAB-based function library for mapping applications to its targeted hardware, the Programmable Pipeline Image Processor (P 2 IP). The P 2 IP is a coarse-grained programmable systolic hardware designed specifically for real-time image and video processing.…”

“…programmable architectures [1,5,16,18]. In this paper, we concentrate on the latter ones having the advantage to increase the overall performance drastically while decreasing computing latency.…”

“…Obviously, they are designed for a specific applicative field. Coarse-grained programmable systolic architectures are used to implement complex vision algorithms, that includes detection of defects on manufactured surfaces [1], street scene understanding [5], object tracking [18] and feature detection [16].…”

Partial Reconfiguration Exploration Over P2IP Architecture

“…In that context, unused PEs still contribute to both, dynamic and static power consumption. For details about mapping each application onto P 2 IP refer to [2].…”

“…It features low-latency systolic array inherent structures, runtime reconfigurable data-path, high-performance CG operators and short compilation times of software applications. Its data path, operating at the pixel clock frequency, can deliver, after the initial latency of a 3-line pipeline, one processed pixel per clock cycle [1,2,3]. The architecture processing core consists of identical Processing Elements (PEs).…”