2006
DOI: 10.1889/1.2433455
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P-5: A-Si TFT Integrated Gate Driver with AC-driven Single Pull-Down Structure

Abstract: A novel gate driver circuit using a-Si TFT has been developed. It has AC driven single pull-down structure for maintaining gate line voltage. Degradation of the circuit is retarded because of relieved stress to the pull-down TFT by alternating the gate node voltage. The circuit has been successfully integrated in 14.1-in. XGA TFT-LCD panel.

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Cited by 28 publications
(23 citation statements)
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“…The lifetime of an a-Si TFT gate driver is determined by the stability of the pull down TFT that is under 50% duty stress at all times [9]. This letter was conducted to extend the lifetime of the pull-down TFT, which determines the lifetime of shift register, by applying reset clock of short-term duty period to the pull-down TFT to compensate for the nonrecovering characteristic of oxide TFTs.…”
Section: Methodsmentioning
confidence: 99%
“…The lifetime of an a-Si TFT gate driver is determined by the stability of the pull down TFT that is under 50% duty stress at all times [9]. This letter was conducted to extend the lifetime of the pull-down TFT, which determines the lifetime of shift register, by applying reset clock of short-term duty period to the pull-down TFT to compensate for the nonrecovering characteristic of oxide TFTs.…”
Section: Methodsmentioning
confidence: 99%
“…The stability of a-Si circuits, which was a barrier to practical use of the technology, has been improved markedly with the invention of the ac-driven pull-down structures so that it is considered no actual problem will occur during everyday usage [1][2][3][4]. The analysis of the failure mechanism and the behavior of clamping voltages back up our assurance [5].…”
Section: Introductionmentioning
confidence: 99%
“…2) In recent times, LCD panel makers are exerting much effort to cut down the unit cost of production, and improve performance as well; thus, they are developing cost reduction technologies such as gate drive ICs embedded in a panel (GIP). [3][4][5] Highly integrated TFTs for GIP, or TFTs in an array for high resolution, require a higher output capability to perform their functions. With this point of view, a reduction in channel length of TFTs can both enhance TFT characteristics and secure marginal areas for panel design.…”
Section: Introductionmentioning
confidence: 99%