P-FMA: A Novel Parameterized Posit Fused Multiply-Accumulate Arithmetic Processor

Jean, Sandra; Raveendran, Aneesh; Selvakumar, Anith; Kaur, Gagandeep; Dharani, Shankar G; Pattanshetty, Shashikala; Desalphine, Vivian

doi:10.1109/vlsid51830.2021.00053

Cited by 8 publications

(3 citation statements)

References 12 publications

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“…The use of 64-bit posits is studied theoretically in [28] and in the initial presentation of this arithmetic [29]. At the hardware level, synthesis results of some posit64 operators are given in [10], [30], [31], and a GEMM accelerator which also supports 64-bit posits is presented in [32]. A more complex architecture with a reconfigurable posit tensor unit supporting posit64 is introduced in [33].…”

Section: Related Workmentioning

confidence: 99%

Big-PERCIVAL: Exploring the Native Use of 64-Bit Posit Arithmetic in Scientific Computing

Mallasén,

Del Barrio,

Prieto-Matias

2024

IEEE Trans. Comput.

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The accuracy requirements in many scientific computing workloads result in the use of double-precision floating-point arithmetic in the execution kernels. Nevertheless, emerging real-number representations, such as posit arithmetic, show promise in delivering even higher accuracy in such computations. In this work, we explore the native use of 64-bit posits in a series of numerical benchmarks and compare their timing performance, accuracy and hardware cost to IEEE 754 doubles. In addition, we also study the conjugate gradient method for numerically solving systems of linear equations in real-world applications. For this, we extend the PERCIVAL RISC-V core and the Xposit custom RISC-V extension with posit64 and quire operations. Results show that posit64 can obtain up to 4 orders of magnitude lower mean square error than doubles. This leads to a reduction in the number of iterations required for convergence in some iterative solvers. However, leveraging the quire accumulator register can limit the order of some operations such as matrix multiplications. Furthermore, detailed FPGA and ASIC synthesis results highlight the significant hardware cost of 64-bit posit arithmetic and quire. Despite this, the large accuracy improvements achieved with the same memory bandwidth suggest that posit arithmetic may provide a potential alternative representation for scientific computing.

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Section: Related Workmentioning

confidence: 99%

Big-PERCIVAL: Exploring the Native Use of 64-Bit Posit Arithmetic in Scientific Computing

Mallasén,

Del Barrio,

Prieto-Matias

2024

IEEE Trans. Comput.

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“…The results demonstrate that the proposed design outperforms previous designs in terms of speed while maintaining reasonable area utilization and power efficiency. [4]This work presents the design and algorithm of a novel parameterized and pipelined Posit fused multiply and accumulate (P-FMA) unit.The P-FMA unit is a fused functional unit that performs addition, subtraction, multiplication, and multiply-and-accumulate operations. The design incorporates a 5-stage pipeline and is parameterized to allow flexibility.…”

Section: Table 21 Posit Regime Decodingmentioning

confidence: 99%

“…Both floating point and posit systems will be evaluated for area, power, and other factors. The goal of designing and testing both a floating point and posit unit is to demonstrate a side-byside comparison so that the costs and benefits of each may be understood.The following is a list of the research tasks [1] to gain an understanding of floating point merits and problems [2] to gain an understanding of posit merits and problems [3] to design floating point and posit arithmetic cores [4] Fully test and analyze both cores and Compare analysis results and discuss.…”

Section: Introductionmentioning

confidence: 99%

Implementation of High Performance Posit-Multiplier

Vinotheni M S,

Karthika K

2023

IJETMS

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To represent real numbers, practically all computer systems now employ IEEE-754 floating point. Posit has recently been offered as an alternative to IEEE-754 floating point because it provides higher accuracy and a wider dynamic range. The use of not-a-numbers (NaN's) is one of the most common , having too many of them wastes valuable bit patterns in floating point format. As an alternative to floating point, a system known as "Universal Numbers'' or UNUMs was developed. There are three variations of this system, but in terms of hardware compatibility, Type III(POSIT) is the best substitute for floating point. By employing only one bit pattern, this approach overcomes the NaN problem associated with floating point format. An IEEE float FPU requires 22.2% more circuitry than a posit processing unit. The proposed posit multiplier consumes 28.5% less power compared to corresponding IEEE Floating point format. The number of posit operations per second(POPS) handled by a device can be ubstantially larger than the number of FLOPS due to lower power consumption. In this paper, High performance Posit multiplier is implemented and compared with normal Floating point multiplier.

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PosAx-O: Exploring Operator-level Approximations for Posit Arithmetic in Embedded AI/ML

Immaneni

Ullah

Nambi

et al. 2022

2022 25th Euromicro Conference on Digital System Design (DSD)

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P-FMA: A Novel Parameterized Posit Fused Multiply-Accumulate Arithmetic Processor

Cited by 8 publications

References 12 publications

Big-PERCIVAL: Exploring the Native Use of 64-Bit Posit Arithmetic in Scientific Computing

Big-PERCIVAL: Exploring the Native Use of 64-Bit Posit Arithmetic in Scientific Computing

Implementation of High Performance Posit-Multiplier

PosAx-O: Exploring Operator-level Approximations for Posit Arithmetic in Embedded AI/ML

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