P4 to FPGA-A Fast Approach for Generating Efficient Network Processors

Abstract

This paper presents a framework for converting P4 programs to VHDL and then implementing them on Field-Programmable Gate Array (FPGA) platforms. In this framework, a match-action-based hardware architecture is introduced with clearly designed components, which correspond to the described functionalities in the P4 programs. A pre-built template library is used for the compilation that includes optimized VHDL templates corresponding to specific clearly designed components. From the output of a standard frontend P4 compiler, the proposed compiler extracts parameters and relationships within the functions being employed, maps them to corresponding templates by calling, configuring, optimizing and instantiating them, and finally generates the appropriate FPGA code. A pre-built evaluation library is also proposed that helps the compiler to optimize the implementation during the mapping phase. A prototype of this framework is also implemented and evaluated; in this process, it is found that the generated processors use few resources and have high throughput and low latency. Compared with a state-of-the-art solution, the packet processing time is halved. In addition, the generated processors are able to operate at a line rate of nearly 100 Gigabits per second for a basic layer-3 forwarding application.

The Future Roadmap of In-Vehicle Network Processing: A HW-Centric (R-)evolution

“…When exploring HW implementations, FPGAs have been identified as a suitable candidate for the prototyping of this architecture since they provide the flexiblity required at system prototyping stages. Some frameworks are available for this purpose such as P4-FPGA [135].…”

“…Safety and Security: Automotive Ethernet in On-Board Diagnosis & in-vehicle networking [26] Cooperation or competition? Coexistence of safety and security in next-generation Ethernet-based automotive networks [42] Secure Automotive On-Board Electronics Network Architecture [101] TSN: Assessments of Real-Time Communications over TSN Automotive Networks [58] Timely Survey of Time-Sensitive Networking: Past and Future Directions [63] DDS and DDS with TSN: DDS middleware on FlexRay network [66] Multi-Level Time-Sensitive Networking Using the Data Distribution Services for Synchronized Three-Phase Measurement Data Transfer [67] Using DDS over TSN to support NATO Generic Vehicle Architecture for Land Systems [68] SDN: OpenFlow [71] Software-Defined Networking in Automotive [72] An In-Vehicle Software Defined Network Architecture for Connected and Automated Vehicles [73] In-Vehicle Software Defined Networking: An Enabler for Data Interoperability [74] Retrofitting SDN to classical in-vehicle networks: SDN4CAN [75] An SDN Architecture for Automotive Ethernet [76] SDN with TSN: SDN-based configuration solution for IEEE 802.1 Time Sensitive Networking [62] Software-Defined Networks Supporting Time-Sensitive In-Vehicular Communication [77] Software-Defined Time Sensitive Networks Configuration and Management [78] SDN for safety applications: Fault-Tolerant Dynamic Scheduling and Routing for TSN based In-vehicle Networks [81] Dynamic Network Reconfiguration in Safety-Critical Aeronautical Systems [82] Service oriented Architecture: A distributed in-vehicle service architecture using dynamically created web Services [83] SODA: Service-Oriented Architecture for Runtime Adaptive Driver Assistance Systems [84] Programmable Dataplane:A Survey on Data Plane Programming with P4[127] An Exhaustive Survey on P4 Programmable Data Plane Switches: Taxonomy, Applications, Challenges, and Future Trend[128] The programmable Data Plane: Abstractions, architectures, algorithms, and applications[129] Modeling and Performance Analysis of P4 Programmable Devices[130] P4 to FPGA-A Fast Approach for Generating Efficient Network Processors[135] One for All, All for One: A Heterogeneous Data Plane for Flexible P4 Processing[149] …”

Hybrid SDN evolution: A comprehensive survey of the state-of-the-art

“…Recently, various solutions to translate P4 programs for traffic processing into Field Programmable Gate Arrays (FPGAs) code have been proposed on the market and in the scientific literature. Among others, we mention Netcope P4 [56], P4FPGA [57], P4→FPGA [58] and P4toFPGA [59]. The main idea behind these initiatives is to combine the high-level P4 programming language with the performance of FPGA-based packet processing.…”

Contributions to the design, development and evaluation of network processors for automotive zonal gateway controllers

“…TSN-Builder: Enabling rapid customization of resource-efficient switches for time-sensitive networking [67] P4 to FPGA-A Fast Approach for Generating Efficient Network Processors [184] Generating VHDL Source Code from UML Models of Embedded System [201] Automation of Domain-specific FPGA-IP Generation and Test [202] DNNBuilder: an Automated Tool for Building High-Performance DNN Hardware Accelerators for FPGAs [203]…”