Package optimization of a stacked die flip chip based test package

Abstract

We report a case study for the optimization of a flip chip based stacked die array test package. We demonstrate the importance of package substrate design and substrate thickness on the processibility and package warpage control. We found that for thin substrates copper balancing of the top and bottom die is crucial. We show the impact of flip chip die thickness and substrate thickness on the die attach of the top die(s) in the stack. Investigations on different top die attach alternatives show that tape die attach can have advantages. We demonstrate the importance of the vertical stack structure (i.e. flip chip thickness) and material selection (i.e. mold compound) on the overall warpage control of the package. The results show that even small changes in the package structure can have large impact on the warpage characteristics of the stacked die package.

Modern IC packaging trends and their reliability implications

“…However within a chip stack warpage requires much tighter control in order to avoid failures. For a flip chip/wirebond stack Pohl et al [6] investigated the factors, which influence the warpage and reliability of the construction. They found that material physics, which includes stress, adhesion, and reliability aspects, must be understood.…”