Package Routing and Thermal Analysis on a Multi-Chip Package (MCP)

This paper describes the thermal characterization and power map methodology on chipset silicon die. The on-die power map affects the overall thermal gradient and heat spreading effect from the die to the package top, which in turns drives the cooling requirements needed to meet package cooling target. This paper demonstrates the power-thermal simulation with different power map resolution and examines its effects on the hot spot on the die.

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Thermal simulation and power map modeling sensitivity study for chipset silicon

Lee

Sasidaran

Cheang

et al. 2007

2007 International Conference on Electronic Materials and Packaging

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A collaborative design from schematic to layout: Based on MCP technology

Pan

Liu

Cao

et al. 2012

2012 13th International Conference on Electronic Packaging Technology &Amp; High Density Packaging

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Package Routing and Thermal Analysis on a Multi-Chip Package (MCP)

Cited by 2 publications

References 1 publication

Thermal simulation and power map modeling sensitivity study for chipset silicon

Thermal simulation and power map modeling sensitivity study for chipset silicon

A collaborative design from schematic to layout: Based on MCP technology

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