Package Stress Monitor to Compensate for the Piezo-Hall Effect in CMOS Hall Sensors

Abstract

Package-induced stress changes the sensitivity of planar Hall plates via the piezo-Hall effect. In this paper, we present a novel stress sensor that allows us to compensate for this undesired mechanical cross-sensitivity. The new CMOScompatible sensor is based on a Wheatstone bridge built of eight appropriately arranged n-and p-doped piezoresistors. The differential output signal V bridge of the sensor is proportional to the sum of in-plane normal stresses σ x x +σ yy with the sensitivity S bridge,σ = ∂ V bridge / V bias /∂ σ x x + σ yy = −0.047GPa −1 . Doping concentrations larger than 10 19 cm −3 for both the n-and p-type resistors are used to minimize the parasitic resistor mismatch due to the junction field effect. Simultaneously, the highly doped resistors keep the relative thermal cross-sensitivity of the sensor as small as 74 ppm K −1 . In contrast to conventional sensor rosettes, the new sensor has the advantage of offering a differential output signal. The measured signal is successfully used to decrease the stress-impact on the sensitivity of CMOS Hall sensors by a factor of five.

A Fully Integrated Hall Sensor Microsystem for Contactless Current Measurement

“…The ASIC includes a fully integrated sensor system which outputs a current and a calibration loop for the sensitivity drift. The correction of the system sensitivity can be done based on the measurement of stress-and temperature-variations [3], [4] or on the measurement of the sensitivity [5]. Within this system the calibration relies on the measurement of the sensitivity and its correction.…”

A Combined Temperature and Stress Sensor in 0.18 μm CMOS Technology

“…For the sake of isotropy wrt. in-plane normal stresses, the two sensors are made of L-shaped resistors (RL), as detailed in [3,5]. The layouts of the sensors are shown in Figure 1b 18 μm CMOS technology.…”

“…This parasitic output signal is subtracted. The resulting offset-free signals Vσ and VT as a function of in-plane stress Δσip and temperature ΔT are described by [3,5] …”

“…However, CMOS temperature sensors are known to suffer from mechanical stress, often referred to as package shift [2]. Similarly, mechanical stress sensors are known to show a parasitic temperature dependence [3].…”

Piezo-Hall effect and fundamental piezo-Hall coefficients of single crystal n-type 3C-SiC(100) with low carrier concentration

“…These stresses can seriously affect the magnetic field sensitivity of Hall devices. The other factors which can introduce drifts in the magnetic field sensitivity of the Hall devices include a thermal mismatch between mounting material and chip in die attachment, mechanical impact during device operation and packaging of fabricated device [5][6][7][8][9] . Consequently, these various types of stresses introduced into the device can induce drifts in device parameters, offset voltage, temperature behavior and finally the magnetic field sensitivity 7 .…”