3D and Circuit Integration of MEMS 2021
DOI: 10.1002/9783527823239.ch17
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Packaging, Sealing, and Interconnection

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“…Wafer-level packaging encapsulates MEMS structures on silicon chips between bonded wafers through surface micromachining and electrical interconnections [8,9]. It has the advantages of low cost, mass production, and high reliability.…”
Section: Introductionmentioning
confidence: 99%
“…Wafer-level packaging encapsulates MEMS structures on silicon chips between bonded wafers through surface micromachining and electrical interconnections [8,9]. It has the advantages of low cost, mass production, and high reliability.…”
Section: Introductionmentioning
confidence: 99%
“…[1] For example, in situ transmission electron microscope (TEM) analysis of gas-phase reactions could profit from gas-tight cavities integrated into a single silicon chip rather than relying on sealing rings or bonding to seal gas between two chips. [2][3][4][5] This reduces potential leaks and saves volume but requires large-area gas-tight cavities that may have the form of free-standing membrane shell structures. [6] In this regard, vapor etch processes and thin, high-quality etch-stop layers set the current standard in achievable aspect ratios as this process is not susceptible to detrimental capillary effects.…”
Section: Introductionmentioning
confidence: 99%