Packet Switching – Queuing Architecture: A Study

Abstract

ABSTRACT:In this paper, the packet switching architecture with output queuing is used. Here the switch is internally non-blocking, but if packets destined to same outputs, output blocking will occur and (even if there are output queues) has a capacity of N*N2 .An exact model of the switch has been developed which can be used to determine the blocking performance of the switch and obtain both its throughput and packet loss characteristics. In this architecture, each line card is connected by a dedicated point to point link to the central switch fabric. Two structures can be classified as Centralized and Distributed. Buffer arrangements are also categorized into output queued and combined input-output queued switches and hardware complexity of OQ, VOQ are also discussed. KEYWORDS:IQ Switches, OQ Switches, VOQ Switches, Switch Fabric. I.INTRODUCTIONOver the past decade, data communication has been revolutionized by a radically new technology called Packet Switching. Packet switched routers need buffers during times of congestion. Buffer arrangements can be placed on inputs and outputs within the switch fabric. A major challenge connected to high-speed switching is related today to switch design that requires the best possible ease of implementation and good performance. The main functions of Switching are: (i) manage packet buffering while selecting packets to transmit each time to avoid contentions and cell loss. (ii) Routing packets from their incoming ports to their destination ports. To avoid contentions and cell loss, the incoming packets are stored in buffers. These buffers can be in inputs, in outputs, in inputs and outputs or shared by inputs and outputs. Although, a lot of existing switches use the shared buffers techniques. In OQ (Output Queue) strategy, all incoming cells at the input are allowed to arrive at the output port and they are served using FIFO (First in First Out) discipline. In this strategy, there is 100% throughput and there is an internal speedup of order of N(impractical for large N) [1].An output buffered switch can be more complex than an input buffered switch because the switch fabric must operate at much higher speed to reduce the probability of cell loss.The IQ (Input Queue) switch can transfer at most one packet from an input and at most one packet to an output in a slot. At the beginning of a slot, more than one HOL (Head of Line Blocking) cells from the input queues have the same destination, and then only one of them is switched and transmitted on the output link in the slot. These switches are easy to implement and throughput is limited to 58.6% under uniform traffic. The other HOL cells continue to be queued at their inputs. Thus, packets in an IQ switch can experience HOL blocking, in which a blocked HOL cell blocks the cells behind it in the input FIFO queue even though the destination ports of these other cells are free and are idling. One of the proposed solution for IQ switches which is VOQ. In this, the main aim is to overcome HOL blocking as there is no speed up require...