PACoGen: A Hardware Posit Arithmetic Core Generator

Jaiswal, Manish Kumar; So, Hayden Kwok-Hay

doi:10.1109/access.2019.2920936

Cited by 79 publications

(53 citation statements)

References 14 publications

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“…In [47] another Posit arithmetic core generator has been introduced, called PACoGEN. The work presents different generators for HDL adder/subtractor and multiplier/division cores.…”

Section: B Hardware Implementations Of the Posit Processing Unitmentioning

confidence: 99%

Novel Arithmetics in Deep Neural Networks Signal Processing for Autonomous Driving: Challenges and Opportunities

Cococcioni

Rossi

Ruffaldi

et al. 2021

IEEE Signal Process. Mag.

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This paper focuses on trends, opportunities and challenges of novel arithmetics for DNN signal processing, with particular reference to assisted and autonomous driving applications. Due to strict constrains in terms of latency, dependability and security of autonomous driving, machine perception (i.e. detection or decisions tasks) based on DNN can not be implemented relying on a remote cloud access. These tasks must be performed in real-time on embedded systems on-board the vehicle, particularly for the inference phase (considering the use of DNNs pre-trained during an off-line step). When developing a DNN computing platform, the choice of the computing arithmetics matters. Moreover, functional safe applications like autonomous driving pose severe constraints on the effect that signal processing accuracy has on final rate of wrong detection/decisions. Hence, after reviewing the different choices and trade-off concerning arithmetics, both in academia and industry, we highlight the issues in implementing DNN accelerators to achieve accurate and low-complex processing of automotive sensor signals (the latter coming from diverse sources like cameras, radars, lidars, ultrasonics). The focus is on both on general-purpose operations massively used in DNN like multiply, accumulation, compare, or on specific functions like for example sigmoid or hyperbolic tangent, used for neuron activation.

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“…In [47] another Posit arithmetic core generator has been introduced, called PACoGEN. The work presents different generators for HDL adder/subtractor and multiplier/division cores.…”

Section: B Hardware Implementations Of the Posit Processing Unitmentioning

confidence: 99%

Novel Arithmetics in Deep Neural Networks Signal Processing for Autonomous Driving: Challenges and Opportunities

Cococcioni

Rossi

Ruffaldi

et al. 2021

IEEE Signal Process. Mag.

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“…1. include the PPU within the processor [21]. This requires the introduction of an additional instruction set and the instrumentation of the compiler.…”

Section: Future Workmentioning

confidence: 99%

Vectorizing posit operations on RISC-V for faster deep neural networks: experiments and comparison with ARM SVE

Cococcioni

Rossi

Ruffaldi³

et al. 2021

Neural Comput & Applic

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With the arrival of the open-source RISC-V processor architecture, there is the chance to rethink Deep Neural Networks (DNNs) and information representation and processing. In this work, we will exploit the following ideas: i) reduce the number of bits needed to represent the weights of the DNNs using our recent findings and implementation of the posit number system, ii) exploit RISC-V vectorization as much as possible to speed up the format encoding/decoding, the evaluation of activations functions (using only arithmetic and logic operations, exploiting approximated formulas) and the computation of core DNNs matrix-vector operations. The comparison with the well-established architecture ARM Scalable Vector Extension is natural and challenging due to its closedness and mature nature. The results show how it is possible to vectorize posit operations on RISC-V, gaining a substantial speed-up on all the operations involved. Furthermore, the experimental outcomes highlight how the new architecture can catch up, in terms of performance, with the more mature ARM architecture. Towards this end, the present study is important because it anticipates the results that we expect to achieve when we will have an open RISC-V hardware co-processor capable to operate natively with posits.

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“…Results are reported in [9] for a Xilinx Zynq-7000, and in [10] for a Virtex 7. We chose for our comparison the simpler setting of [9] (Zynq-7000, no pipeline) and synthesized both our library and that of [10] 4 for this setting. Results are given in Table II.…”

Section: A Comparison With the State-of-the-artmentioning

confidence: 99%

“…However, the hardware cost of posits is not yet completely known. Hardware posit adders and multipliers have been written in HDL [9], [10] or using Intel OpenCL SDK compliant templatized C++ operators [11]. Using posits as a storage format by decoding/encoding from/to a large enough IEEE floating-point format as also been studied in [5].…”

Section: Introductionmentioning

confidence: 99%

Evaluating the Hardware Cost of the Posit Number System

Uguen

Forget

Dinechin

2019

2019 29th International Conference on Field Programmable Logic and Applications (FPL)

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The posit number system is proposed as a replacement of IEEE floating-point numbers. It is a floating-point system that trades exponent bits for significand bits, depending on the magnitude of the numbers. Thus, it provides more precision for numbers around 1, at the expense of lower precision for very large or very small numbers. Several works have demonstrated that this trade-off can improve the accuracy of applications. However, the variable-length exponent and significand encoding impacts the hardware cost of posit arithmetic. The objective of the present work is to enable application-level evaluations of the posit system that include performance and resource consumption. To this purpose, this article introduces an open-source hardware implementation of the posit number system, in the form of a C++ templatized library compatible with Vivado HLS. This library currently implements addition, subtraction and multiplication for custom-size posits. In addition, the posit standard also mandates the presence of the "quire", a large accumulator able to perform exact sums of products. The proposed library includes the first open-source parameterized hardware quire. This library is shown to improve the state-of-the-art of posit implementations in terms of latency and resource consumption. Still, standard 32 bits posit adders and multipliers are found to be much larger and slower than the corresponding floatingpoint operators. The cost of the posit 32 quire is shown to be comparable to that of a Kulisch accumulator for 32 bits floatingpoint.

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PACoGen: A Hardware Posit Arithmetic Core Generator

Cited by 79 publications

References 14 publications

Novel Arithmetics in Deep Neural Networks Signal Processing for Autonomous Driving: Challenges and Opportunities

Novel Arithmetics in Deep Neural Networks Signal Processing for Autonomous Driving: Challenges and Opportunities

Vectorizing posit operations on RISC-V for faster deep neural networks: experiments and comparison with ARM SVE

Evaluating the Hardware Cost of the Posit Number System

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