Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2014 2014
DOI: 10.7873/date.2014.385
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Panel: Future SoC verification methodology: UVM evolution or revolution?

Abstract: With increasing design complexity System on Chip (SoC) verification is becoming a more and more important and challenging aspect of the overall development process. The Universal Verification Methodology (UVM) is thereby a common solution to this problem; although it still keeps some problems unsolved. In this panel leading experts from industry (both users and vendors) and academy will discuss the future of SoC verification methodology.

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Cited by 3 publications
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“…An example on how useful the standard can be in a system-level, Universal Verication Methodology (UVM) [81] compatible, verication environment is the way CPU registers can be easily mapped and converted to SystemVerilog models, by using the meta-data information provided for the registers in IP-XACT format [26]. While SysPy already provides tools for building and simulating a SoC, with the addition of the IP-XACT generation feature it proves its ability to be compatible with all the industry standards related to digital hardware design and verication.…”
Section: Ip-xact Modelsmentioning
confidence: 99%
“…An example on how useful the standard can be in a system-level, Universal Verication Methodology (UVM) [81] compatible, verication environment is the way CPU registers can be easily mapped and converted to SystemVerilog models, by using the meta-data information provided for the registers in IP-XACT format [26]. While SysPy already provides tools for building and simulating a SoC, with the addition of the IP-XACT generation feature it proves its ability to be compatible with all the industry standards related to digital hardware design and verication.…”
Section: Ip-xact Modelsmentioning
confidence: 99%