ParaHist: FPGA Implementation of Parallel Event-Based Histogram for Optical Flow Calculation

Pivezhandi, Mohammad; Jones, Phillip H.; Zambreno, Joseph

doi:10.1109/asap49362.2020.00038

Cited by 4 publications

(1 citation statement)

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“…The Farneback optical flow algorithm is widely used in computer vision and is supported by numerous implementations in C, MATLAB, and as a function in OpenCV. In this study, mature C code was used, with modifications made for compatibility with High-Level Synthesis (HLS) [13], including optimizations for language compatibility, data types, functions, loops, and arrays. HLS simulation was used to evaluate the hardware resource utilization of the Intellectual Property (IP) core, with changes in resource usage before and after optimization shown in Table 1 a high resource utilization rate and poor real-time performance.…”

Section: Discussion On the Advantages And Limitations Of The Farnebac...mentioning

confidence: 99%

Real-time FPGA Implementation of an Optic Flow Algorithm Suitable for Background Oriented Schlieren Technique

Wang,

Luo,

et al. 2024

J. Phys.: Conf. Ser.

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To meet the demands of real-time displacement detection in embedded systems, a real-time optical flow calculation method suitable for background oriented schlieren (BOS) technology was transplanted and implemented on an Field Programmable Gate Array(FPGA) system. Firstly, through the analysis of different optical flow operation characteristics and the comparison of processing results in MATLAB with actual experimental data, an optical flow algorithm suitable for real-time processing of background shadow images was selected. Subsequently, by using hardware pipelining and multimodule parallel processing, the single-layer L&K optical flow algorithm was transplanted onto the FPGA and algorithm optimization was performed to achieve real-time optical flow calculation based on adjacent frame images. The key optimization techniques in this paper mainly include cleverly designing Double-Data-Rate Three Synchronous Dynamic Random Access Memory (DDR3) memory partitioning read and write logic to avoid image read and write conflicts; ensuring the timing alignment and data synchronization of consecutive frames by using burst read arbitration modules and two independent First In First Out (FIFO) buffers; and in optical flow calculation, constructing a 3×3 window using a shifting FIFO method to effectively save cache resources and improve computational speed. Experimental results show that the system can achieve real-time processing speeds of not less than 60fps for 1024×768 resolution images, meeting the requirements of practical applications.

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Section: Discussion On the Advantages And Limitations Of The Farnebac...mentioning

confidence: 99%