ParaLarPD: Parallel FPGA Router Using Primal-Dual Sub-Gradient Method

Agrawal, Rohit; Ahuja, Kapil; Hoo, Chin Hau; Nguyen, Tuan D. A.; Kumar, Akash

doi:10.3390/electronics8121439

Cited by 9 publications

(31 citation statements)

References 18 publications

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“…There are two other important metrics used to determine the efficiency of the FPGA routing process; the total wire length and the critical path delay, with the later one being more easily measurable. In [4], we showed that on an average, ParaLarPD achieved the same total wire length but a slightly deteriorated critical path delay when compared with ParaLaR.…”

Section: Introductionmentioning

confidence: 87%

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ParaLarH: Parallel FPGA Router based upon Lagrange Heuristics

Agrawal,

Ahuja,

Maheshwari

et al. 2020

Preprint

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Routing of the nets in Field Programmable Gate Array (FPGA) design flow is one of the most time consuming steps. Although Versatile Place and Route (VPR), which is a commonly used algorithm for this purpose, routes effectively, it is slow in execution. One way to accelerate this design flow is to use parallelization. Since VPR is intrinsically sequential, a set of parallel algorithms have been recently proposed for this purpose (ParaLaR and ParaLarPD).These algorithms formulate the routing process as a Linear Program (LP) and solve it using the Lagrange relaxation, the sub-gradient method, and the Steiner tree algorithm. Out of the many metrics available to check the effectiveness of routing, ParaLarPD, which is an improved version of ParaLaR, suffers from large violations in the constraints of the LP problem (which is related to the minimum channel width metric) as well as an easily measurable critical path delay metric that can be improved further.In this paper, we introduce a set of novel Lagrange heuristics that improve the Lagrange relaxation process. When tested on the MCNC benchmark circuits, on an average, this leads to halving of the constraints violation, up to 10% improvement in the minimum channel width, and up to 8% reduction in the critical path delay as obtained from ParaLarPD. We term our new algorithm as ParaLarH. Due to the increased work in the Lagrange relaxation process, as compared to ParaLarPD, ParaLarH does slightly deteriorate the speedup obtained because of parallelization, however, this aspect is easily compensated by using more number of threads.

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Section: Introductionmentioning

confidence: 87%

“…In one of our recent works [4], we substantially improved the constraints violation drawback of Par-aLaR. We achieved this by developing a more problem specific version of the sub-gradient method and fine tuning the size of its iterative step.…”

Section: Introductionmentioning

confidence: 99%

ParaLarH: Parallel FPGA Router based upon Lagrange Heuristics

Agrawal,

Ahuja,

Maheshwari

et al. 2020

Preprint

Self Cite

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“…Next, we give a brief idea of LASSO and ADMM, which we use. The general LASSO problem is given as [45]

\min_{z} \{\frac{1}{2} {false∥ A z - b false∥}_{2}^{2} + λ {false∥ z false∥}_{1}\},

where

z \in {double-struckR}^{n}

A \in {double-struckR}^{p \times n}

b \in {double-struckR}^{p}

{false∥ \cdot false∥}_{2}

is the

ℓ_{2}

norm and

λ > 0

is a scalar regularization parameter also called Lagrangian parameter [46]. Further, () is transformed into a form solvable by ADMM [44].…”

Section: Compressed Sensingmentioning

confidence: 99%

“…where z ∈ ℝ n , A ∈ ℝ p×n , b ∈ ℝ p , ‖ ⋅ ‖ 2 is the 2 norm and > 0 is a scalar regularization parameter also called Lagrangian parameter [46]. Further, ( 7) is transformed into a form solvable by ADMM [44].…”

Section: Reconstruction Of the Approximate Signalmentioning

confidence: 99%

CSIS: Compressed sensing‐based enhanced‐embedding capacity image steganography scheme

Agrawal

Ahuja

2021

IET Image Processing

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Image steganography plays a vital role in securing secret data by embedding it in the cover images. Usually, these images are communicated in a compressed format. Existing techniques achieve this but have low embedding capacity. Hence, the goal here is to enhance the embedding capacity while preserving the visual quality of the stego-image. It is also intended to ensure that the scheme is resistant to steganalysis attacks. This paper proposes a compressed sensing image steganography (CSIS) scheme to achieve these goals. In CSIS, the cover image is sparsified block-wise, linear measurements are obtained, and then permissible measurements are selected. Next, the secret data is encrypted, and 2 bits of this encrypted data are embedded into each permissible measurement. For the reconstruction of the stego-image, ADMM and LASSO are used for the resultant optimization problem. Experiments are performed on several standard greyscale images and a colour image. Higher embedding capacity, 1.53 times more compared to the most recent scheme, is achieved. An average of 37.92 dB PSNR value, and average values close to 1 for both the mean SSIM index and the NCC coefficients are obtained, which is considered good. These metrics show that CSIS substantially outperforms existing similar steganography schemes. This is an open access article under the terms of the Creative Commons Attribution License, which permits use, distribution and reproduction in any medium, provided the original work is properly cited.

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“…To diminish the required internal occupied resources, it is necessary to take into account specifics of logic elements implementing FSM circuits [8,9]. Nowadays, field programmable gate arrays (FPGAs) [10][11][12] are widely used in the implementation of digital systems [9,[13][14][15]. Due to it, we choose FPGA-based FSMs as a research object in the given article.…”

Section: Introductionmentioning

confidence: 99%

Reducing LUT Count for FPGA-Based Mealy FSMs

2020

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Very often, digital systems include sequential blocks which can be represented using a model of Mealy finite state machine (FSM). It is very important to improve such FSM characteristics as the number of used logic elements, operating frequency and power consumption. The paper proposes a novel design method optimizing LUT counts of LUT-based Mealy FSMs. The method is based on simultaneous use of such methods of structural decomposition as the replacement of FSM inputs and encoding of the collections of outputs. The proposed method results in three-level logic circuits of Mealy FSMs. These circuits have regular systems of interconnections. An example of FSM synthesis with the proposed method is given. The experiments with standard benchmarks were conducted. The results of experiments show that the proposed approach leads to reducing the LUT counts from 12% to 59% in average compared with known methods of synthesis of single-level FSMs. Furthermore, our approach provides better LUT counts as compared to methods of synthesis of two-level FSMs (from 9% to 20%). This gain is accompanied by a small loss of FSM performance.

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ParaLarPD: Parallel FPGA Router Using Primal-Dual Sub-Gradient Method

Cited by 9 publications

References 18 publications

ParaLarH: Parallel FPGA Router based upon Lagrange Heuristics

ParaLarH: Parallel FPGA Router based upon Lagrange Heuristics

CSIS: Compressed sensing‐based enhanced‐embedding capacity image steganography scheme

Reducing LUT Count for FPGA-Based Mealy FSMs

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