Parallel architecture for real time computation of discrete Mellin transform

Abstract

In this paper, a parallel architecture for the computation of one dimensional discrete Mellin transform (DMT) is proposed for real time hardware implementation. Since Mellin transform is a useful technique in pattern recognition, speech processing, image registration and signal detection due to its scale invariant property, so it is essential to develop VLSI architecture of this transformation for hardware implementation in real time applications. The proposed parallel architecture for one dimensional DMT is based on ROM and MAC(Multiply and Accumulator), which is designed using verilog hardware description language, and further synthesized using Xilinx synthesis tool(XST) targeting the commercially available Xilinx FPGA device "XC3SPQ208". Synthesis result shows that it can be operated at a clock frequency of 32MHz making it suitable for real time applications.