Parallel architecture of power‐of‐two multipliers for FPGAs

Abstract

This research work presents a novel approach to design efficient power-of-two multipliers on modern fieldprogrammable gate arrays (FPGA) devices. Several ways of exploiting fixed-point power-of-two multiplications have been recently demonstrated to reduce the computational complexity of several computationally intensive applications, such as computer vision, deep learning, and many others. Modern FPGA devices provide speed-optimised intellectual property (IP) cores based on embedded modules, such as digital signal processing blocks, and area-optimised IP cores based on reconfigurable logic resources, such as look-up tables and flip-flops. Unfortunately, due either to their limited available amount or to their limited running frequency, these IP cores do not allow the overall computational capability offered by an FPGA device to be completely exploited. While the speed-optimised version of the multiplier proposed here is fast enough to increase the number of operations performed per second by up to 4.3 times, with respect to the conventional designs, its area-optimised implementation reduces resources requirements and energy consumption by up to 22 and 40%.

A Fresh Design of Power Effective Adapted Vedic Multiplier for Modern Digital Signal Processors

“…In the two's complement high-performance multiplier, the opposing sign transfers to the nal [15]. Fig.2.9.…”

A Fresh Design of Power Effective Adapted Vedic Multiplier for Modern Digital Signal Processors

“…In the two's complement high-performance multiplier, the opposing sign transfers to the nal [15]. Figure 2.7 shows the RTL schematic for 2's complements high-performance multiplier.…”