Parallel architectures for the kNN classifier -- design of soft IP cores and FPGA implementations

Stamoulias, Ioannis; Μανωλάκος, Ηλίας Σ.

doi:10.1145/2514641.2514649

Cited by 28 publications

(9 citation statements)

References 18 publications

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“…There have been several proposed architectures that accelerate machine learning algorithms [21,30,[34][35][36][37][38][39][40][41][42][43][44][45][46]. However, TABLA fundamentally differs from these works, as it is not an accelerator.…”

Section: Related Workmentioning

confidence: 99%

TABLA: A unified template-based framework for accelerating statistical machine learning

Mahajan

Park

Amaro

et al. 2016

2016 IEEE International Symposium on High Performance Computer Architecture (HPCA)

138

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A growing number of commercial and enterprise systems increasingly rely on compute-intensive machine learning algorithms. While the demand for these compute-intensive applications is growing, the performance benefits from general-purpose platforms are diminishing. Field Programmable Gate Arrays (FP-GAs) provide a promising path forward to accommodate the needs of machine learning algorithms and represent an intermediate point between the efficiency of ASICs and the programmability of general-purpose processors. However, acceleration with FPGAs still requires long design cycles and extensive expertise in hardware design. To tackle this challenge, instead of designing an accelerator for machine learning algorithms, we develop TABLA, a framework that generates accelerators for a class of machine learning algorithms. The key is to identify the commonalities across a wide range of machine learning algorithms and utilize this commonality to provide a high-level abstraction for programmers. TABLA leverages the insight that many learning algorithms can be expressed as stochastic optimization problems. Therefore, a learning task becomes solving an optimization problem using stochastic gradient descent that minimizes an objective function. The gradient solver is fixed while the objective function changes for different learning algorithms. TABLA provides a templatebased framework for accelerating this class of learning algorithms. With TABLA, the developer uses a high-level language to only specify the learning model as the gradient of the objective function. TABLA then automatically generates the synthesizable implementation of the accelerator for FPGA realization.We use TABLA to generate accelerators for ten different learning task that are implemented on a Xilinx Zynq FPGA platform. We rigorously compare the benefits of the FPGA acceleration to both multicore CPUs (ARM Cortex A15 and Xeon E3) and to many-core GPUs (Tegra K1, GTX 650 Ti, and Tesla K40) using real hardware measurements. TABLA-generated accelerators provide 15.0× and 2.9× average speedup over the ARM and the Xeon processors, respectively. These accelerators provide 22.7×, 53.7×, and 99.2× higher performance-per-Watt compare to Tegra, GTX 650, and Tesla, respectively. These benefits are achieved while the programmers write less than 50 lines of code.

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Section: Related Workmentioning

confidence: 99%

TABLA: A unified template-based framework for accelerating statistical machine learning

Mahajan

Park

Amaro

et al. 2016

2016 IEEE International Symposium on High Performance Computer Architecture (HPCA)

138

View full text Add to dashboard Cite

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“…First, previous FPGA designs are generally built for specific distance-related algorithm and hardware. For example, works from [4][5][6] target on KNN FPGA acceleration, while researches from [7,13,14] focus on K-means. Moreover, previous designs [4,5] usually assume that dataset can be fully fit into the FPGA on-chip memory, and they are only evaluated on a limited number of small datasets, for example, in [5], Kmeans acceleration is evaluated on a micro-array dataset with only 2,905 points.…”

Section: B Hardware Accelerationmentioning

confidence: 99%

“…The second problem with previous works is that they fail to incorporate algorithmic optimizations in the hardware design. For example, works from [4,6,7,13], directly port the standard K-means and KNN algorithms to FPGA, and only apply hardware-level optimization. One exception is a recent work [22], which promotes to combine TI optimization and FPGA acceleration for K-means.…”

Section: B Hardware Accelerationmentioning

confidence: 99%

“…Count on FPGAs as the only source of acceleration. Previous works [4,7,[13][14][15][16] place the whole algorithm on the FPGA accelerator without considering the assists from the computing resource on the host CPU. As a result, their designs are usually limited by the on-chip memory and computing elements, and cannot fully exploit the power of the FPGA.…”

Section: Introductionmentioning

confidence: 99%

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AccD: A Compiler-based Framework for Accelerating Distance-related Algorithms on CPU-FPGA Platforms

Wang¹,

Feng²,

Li³

et al. 2019

Preprint

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As a promising solution to boost the performance of distance-related algorithms (e.g., K-means and KNN), FPGAbased acceleration attracts lots of attention, but also comes with numerous challenges. In this work, we propose AccD, a compiler-based framework for accelerating distance-related algorithms on CPU-FPGA platforms. Specifically, AccD provides a Domain-specific Language to unify distance-related algorithms effectively, and an optimizing compiler to reconcile the benefits from both the algorithmic optimization on the CPU and the hardware acceleration on the FPGA. The output of AccD is a high-performance and power-efficient design that can be easily synthesized and deployed on mainstream CPU-FPGA platforms. Intensive experiments show that AccD designs achieve 31.42× speedup and 99.63× better energy efficiency on average over standard CPU-based implementations.

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“…They report as the main shortcomings of these works that they are not general-purpose, perform classification of only one sample at a time, work with custom fixed-point numerical representation, and require considerable design changes when there are changes in the parameters or the dataset. Works focused on the implementation of general-purpose KNN accelerators can be found in [20,21,25].…”

Section: Introductionmentioning

confidence: 99%

A Modified KNN Algorithm for High-Performance Computing on FPGA of Real-Time m-QAM Demodulators

2021

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A methodology for scalable and concurrent real-time implementation of highly recurrent algorithms is presented and experimentally validated using the AWS-FPGA. This paper presents a parallel implementation of a KNN algorithm focused on the m-QAM demodulators using high-level synthesis for fast prototyping, parameterization, and scalability of the design. The proposed design shows the successful implementation of the KNN algorithm for interchannel interference mitigation in a 3 × 16 Gbaud 16-QAM Nyquist WDM system. Additionally, we present a modified version of the KNN algorithm in which comparisons among data symbols are reduced by identifying the closest neighbor using the rule of the 8-connected clusters used for image processing. Real-time implementation of the modified KNN on a Xilinx Virtex UltraScale+ VU9P AWS-FPGA board was compared with the results obtained in previous work using the same data from the same experimental setup but offline DSP using Matlab. The results show that the difference is negligible below FEC limit. Additionally, the modified KNN shows a reduction of operations from 43 percent to 75 percent, depending on the symbol’s position in the constellation, achieving a reduction 47.25% reduction in total computational time for 100 K input symbols processed on 20 parallel cores compared to the KNN algorithm.

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Parallel architectures for the kNN classifier -- design of soft IP cores and FPGA implementations

Cited by 28 publications

References 18 publications

TABLA: A unified template-based framework for accelerating statistical machine learning

TABLA: A unified template-based framework for accelerating statistical machine learning

AccD: A Compiler-based Framework for Accelerating Distance-related Algorithms on CPU-FPGA Platforms

A Modified KNN Algorithm for High-Performance Computing on FPGA of Real-Time m-QAM Demodulators

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