Parallel CLA algorithm for fast addition

Manzoul, Mahmoud A.

doi:10.1109/pcee.2000.873601

Cited by 4 publications

(6 citation statements)

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“…To optimize the speed, we joined two FAs in a single block and use the carry look-ahead technique [19] to shorten the carry path within the radix-4 FA block. The block diagram of the proposed radix-4 FA is shown in Fig.…”

Section: Basic Radix-4 Famentioning

confidence: 99%

“…We use the strategy presented in [2] to construct a variable block size CSEL optimized for speed. The size of first and second block is computed by equation (19). (19) where M 1,2opt is rounded to nearest integer.…”

Section: Carry Select Addermentioning

confidence: 99%

“…The size of first and second block is computed by equation (19). (19) where M 1,2opt is rounded to nearest integer. In (19) where τ int is the intrinsic delay of the multiplexer, τ FO is increase in multiplexer delay when fan-out is increased by 1, and τ carry is the carry propagation delay of a FA.…”

Section: Carry Select Addermentioning

confidence: 99%

“…Values for α and β are 0.528 and 0.0955, respectively. Block sizes for the adder are obtained from equations (19) and (20) and given in Table 5. We obtain a nearly optimum CSEL [2] with N * = 31.…”

Section: Constructing An Optimum Csel Using Radix-2 Famentioning

confidence: 99%

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Performance analysis of radix-4 adders

Asif

Vesterbacka

2012

Integration

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Abstract-We present a radix-4 static CMOS full adder circuit that reduces the propagation delay, PDP, and EDP in carrybased adders compared with using a standard radix-2 full adder solution. The improvements are obtained by employing carry look-ahead technique at the transistor level. Spice simulations using 45 nm CMOS technology parameters with a power supply voltage of 1.1 V indicate that the radix-4 circuit is 24% faster than a 2-bit radix-2 ripple carry adder with slightly larger transistor count, whereas the power consumption is almost the same. A second scheme for radix-2 and radix-4 adders that have a reduced number of transistors in the carry path is also investigated. Simulation results also confirm that the radix-4 adder gives better performance as compared to a standard 2-bit CLA. 32-bit ripple carry, 2-stage carry select, variable size carry select, and carry skip adders are implemented with the different full adders as building blocks. There are PDP savings, with one exception, for the 32-bit adders in the range 8% to 18% and EDP savings in the range 21% to 53% using radix-4 as compared to radix-2.

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Section: Basic Radix-4 Famentioning

confidence: 99%

Section: Carry Select Addermentioning

confidence: 99%

Section: Carry Select Addermentioning

confidence: 99%

Section: Constructing An Optimum Csel Using Radix-2 Famentioning

confidence: 99%

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Performance analysis of radix-4 adders

Asif

Vesterbacka

2012

Integration

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“…According to above analysis, the production of P 4k+j , Q 4k+j need one gate level , the production of PX 4k+3 、 4k , QX 4k+3 、 4k need two gates levels, production of C 4k+j needs two gates levels [9] , production of C 4k+3 needs two gates levels, function S i needs two gates levels. Therefore, n-adder gate delay time is [10] :…”

Section: Hierarchical Cluster Analysis Of Licmentioning

confidence: 99%

The Research of Large Numbers Adder to Rapid Realization Method

Fang

Tinggang²,

Han³

et al. 2008

2008 IEEE Pacific-Asia Workshop on Computational Intelligence and Industrial Application

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This paper has presented a method of carry forecast between groups to improve the speed of the large numbers adder in some cryptography and other applications. Firstly, the large numbers is divided into many groups, in which the delay of carry-chain is reduced by Carry look-ahead; second, the group addition operation is finished by carry forecast between groups; lastly, the addition sum of different carry forecast state was selected as the final result basing on the carry state. The delay of the large numbers addition which data width is more than 1024-bit is constantly 19 gate levels. Because of the carry transferring is translated into the carry state equation comparison, the carry delay of adder is not changing with the increasing of data width.

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Histogram algorithm and its circuit design based on parallel computing for quantum video

Zhang,

Lu,

et al. 2024

Multimed Tools Appl

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Parallel CLA algorithm for fast addition

Cited by 4 publications

References 1 publication

Performance analysis of radix-4 adders

Performance analysis of radix-4 adders

The Research of Large Numbers Adder to Rapid Realization Method

Histogram algorithm and its circuit design based on parallel computing for quantum video

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