Parallel double error correcting code design to mitigate multi-bit upsets in SRAMs

Naseer, R.; Draper, J.

doi:10.1109/esscirc.2008.4681832

Cited by 115 publications

(43 citation statements)

References 10 publications

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“…In order to evaluate system performance, instruction per-cycle (IPC) for cache line sizes of 1024 bits and 512 bits are plotted in Figure 12. In our evaluation, we add zero cycle latency for parity code, one cycle latency for SECDED, two cycle latencies for DECTED, and seven cycle latencies for 4EC5ED [23,33]. As shown in the figure, the proposed two-layer ECCs achieves similar IPC with 8-way SECDED and 16-way SECDED because the two-layer ECCs only requires simple parity code encoding / decoding processes for most cache accesses.…”

Section: Performance Degradationmentioning

confidence: 89%

Two-Layer Error Control Codes Combining Rectangular and Hamming Product Codes for Cache Error

Zhang

Ampadu

2014

JLPEA

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Abstract:We propose a novel two-layer error control code, combining error detection capability of rectangular codes and error correction capability of Hamming product codes in an efficient way, in order to increase cache error resilience for many core systems, while maintaining low power, area and latency overhead. Based on the fact of low latency and overhead of rectangular codes and high error control capability of Hamming product codes, two-layer error control codes employ simple rectangular codes for each cache line to detect cache errors, while loading the extra Hamming product code checks bits in the case of error detection; thus enabling reliable large-scale cache operations. Analysis and experiments are conducted to evaluate the cache fault-tolerant capability of various existing solutions and the proposed approach. The results show that the proposed approach can significantly increase Mean-Error-To-Failure (METF) and Mean-Time-To-failure (MTTF) up to 2.8×, reduce storage overhead by over 57%, and increase instruction per-cycle (IPC) up to 7%, compared to complex four-way 4EC5ED; and it increases METF and MTTF up to 133×, reduces storage overhead by over 11%, and achieves a similar IPC compared to simple eight-way single-error correcting double-error detecting (SECDED). The cost of the proposed approach is no more than 4% external memory access overhead.

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Section: Performance Degradationmentioning

confidence: 89%

Two-Layer Error Control Codes Combining Rectangular and Hamming Product Codes for Cache Error

Zhang

Ampadu

2014

JLPEA

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“…Results of irradiation tests on 90nm commercial processes reveal that multi-bit upsets as large as 13 bits can occur in sub-100nm technologies [18]. These faults are expected to increase in the future processors due to shrinking size of the transistors.…”

Section: Multi-bit Faultsmentioning

confidence: 99%

FIMSIM: A fault injection infrastructure for microarchitectural simulators

Yalcin

Unsal

Cristal

et al. 2011

2011 IEEE 29th International Conference on Computer Design (ICCD)

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Abstract-Fault injection is a widely used approach for experiment-based dependability evaluation in which faults can be injected to the hardware, to the simulator or to the software. Simulation based fault injection is more appealing for researchers, since it can be utilized at the early design stage of the processor. As such, it enables a preliminary analysis of the correlation between the criticality of circuit level faults and their impact on applications. However, the lack of publicly available fault injectors for microarchitecture level simulators brings extra burden of designing and implementing fault injectors to the researchers who evaluate microarchitecture dependability. In this study, we present FIMSIM, to the best of our knowledge, the first publicly available fault injection simulator at the microarchitecture level. FIMSIM is a compact tool which is capable of injecting transient, permanent, intermittent and multi-bit faults. Therefore, FIMSIM provides the opportunity to comprehensively evaluate the vulnerability of different microarchitectural structures against different fault models.

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“…In addition, different error-correction codes can introduce extra access cycles because of critical time overhead introduced by encoding/decoding process. In our evaluation, we add onecycle latency for SECDED, two-cycle latency for DECTED, and seven-cycle latency for 4EC5ED [5], [18]. To evaluate system performance of various mechanisms, Fig.…”

Section: Ipc Performance Comparisonmentioning

confidence: 99%

Reliable Ultra-Low-Voltage Cache Design for Many-Core Systems

Zhang

Stojanović

Ampadu

2012

IEEE Trans. Circuits Syst. II

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Abstract-We reduce cache supply voltage below the normally acceptable V DDM IN , in order to improve overall manycore system energy efficiency. Based on the observation that cache lines contain mostly one hard faulty cell at these ultralow supply voltages, we exploit existing double-error correcting triple-error detecting codes, together with cache line disabling, to handle both soft and hard cache faults, thus enabling reliable ultra-low supply voltage cache operation. Compared to the nextbest approach in the research literature, the proposed method reduces system energy consumption by up to 25% and energyexecution time product by nearly 10%, while introducing only 0.28% storage overhead and marginal instruction per cycle degradation, when the target yield loss rate is 1/1000.

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Parallel double error correcting code design to mitigate multi-bit upsets in SRAMs

Cited by 115 publications

References 10 publications

Two-Layer Error Control Codes Combining Rectangular and Hamming Product Codes for Cache Error

Two-Layer Error Control Codes Combining Rectangular and Hamming Product Codes for Cache Error

FIMSIM: A fault injection infrastructure for microarchitectural simulators

Reliable Ultra-Low-Voltage Cache Design for Many-Core Systems

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