Parallel function invocation in a dynamic argument-fetching dataflow architecture

Abstract

This paper outlines the basic structure of a dynamic dataflow architecture based on the argument-fetching dataflow principle(41. In particular, we present a scheme to exploit fine-grain parallelism in function invocation based on the argument-fetching principle. We extend the static architecture by associating a frame of consecutive memory space for each parallel function invocation, called a function overlay, and identify each invocation instance with the base address of its overlay. Furthermore, our scheme gains efficiency by making effective use of the power provided by the argument-fetching dataflow principle: the separation of the instruction scheduling mechanism and their execution. While no loop unravelling is allowed, the architecture inherits the power of dataflow software pipelining[5] from the static architecture. The proposed architecture will have a memory overlay manager separate from the pipelined execution unitto handle function applications and memory management. To verify our design, a set of standard benchmark programs were mapped onto the new architecture and executed on an experimental general-purpose dataflow architecture simulation testbed.

An Implementation of the Codelet Model

“…The address of a codelet is required to signal codelets outside a TP, and can be provided at runtime. DARTS implements a form of argument fetching dataflow [10], as the act of signaling is dissociated from passing data. For this reason data is written first, and then a codelet is signaled.…”