Parallel graph traversal for FPGA

Ni, Shice; Dou, Yong; Zou, Dan; Li, Rongchun; Wang, Qiang

doi:10.1587/elex.11.20130987

Cited by 6 publications

(4 citation statements)

References 6 publications

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“…As an important algorithm, the computation of BFS is extensively studied in various platforms, including CPUs [12], [13], GPUs [14], [15], and FPGAs [16], [17], [18], [19], [20], [21], [3], [5], [22], [9], [23]. We briefly survey the relevant works in FPGA-based BFS accelerators below.…”

Section: Related Workmentioning

confidence: 99%

ScalaBFS: A Scalable BFS Accelerator on FPGA-HBM Platform

Liu

Shao

et al. 2021

The 2021 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

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High Bandwidth Memory (HBM) provides massive aggregated memory bandwidth by exposing multiple memory channels to the processing units. To achieve high performance, an accelerator built on top of an FPGA configured with HBM (i.e., FPGA-HBM platform) needs to scale its performance according to the available memory channels. In this paper, we propose an accelerator for BFS (Breadth-First Search) algorithm, named as ScalaBFS, that builds multiple processing elements to sufficiently exploit the high bandwidth of HBM to improve efficiency. We implement the prototype system of ScalaBFS and conduct BFS in both real-world and synthetic scale-free graphs on Xilinx Alveo U280 FPGA card (real hardware). The experimental results show that ScalaBFS scales its performance almost linearly according to the available memory pseudo channels (PCs) from the HBM2 subsystem of U280. By fully using the 32 PCs and building 64 processing elements (PEs) on U280, ScalaBFS achieves a performance up to 19.7 GTEPS (Giga Traversed Edges Per Second). When conducting BFS in sparse real-world graphs, ScalaBFS achieves equivalent GTEPS to Gunrock running on the state-of-art Nvidia V100 GPU that features 64-PC HBM2 (twice memory bandwidth than U280).

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Section: Related Workmentioning

confidence: 99%

ScalaBFS: A Scalable BFS Accelerator on FPGA-HBM Platform

Liu

Shao

et al. 2021

The 2021 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

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“…The solution issues many parallel memory requests and decouples memory access and execution units. Ni et al accelerate BFS by applying a horizontal partitioning allowing to distribute the graph and its associated metadata over multiple memory channels [92]. In this way, multiple PEs can traverse the graph in parallel utilizing a high memory bandwidth.…”

Section: Compressed Sparse Row (Csr)mentioning

confidence: 99%

“…This is a meta-pattern that can be combined with any of the aforementioned patterns. One example of using multiple channels is placing different data structures on different channels [75,92].…”

Section: Accelerator Placementmentioning

confidence: 99%

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Non-Relational Databases on FPGAs: Survey, Design Decisions, Challenges

Dann¹,

Ritter²,

Fröning³

2020

Preprint

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Non-relational database systems (NRDS), such as graph, document, key-value, and wide-column, have gained much attention in various trending (business) application domains like smart logistics, social network analysis, and medical applications, due to their data model variety and scalability. The broad data variety and sheer size of datasets pose unique challenges for the system design and runtime (incl. power consumption). While CPU performance scaling becomes increasingly more difficult, we argue that NRDS can benefit from adding field programmable gate arrays (FPGAs) as accelerators. However, FPGA-accelerated NRDS have not been systematically studied, yet.To facilitate understanding of this emerging domain, we explore the fit of FPGA acceleration for NRDS with a focus on data model variety. We define the term NRDS class as a group of non-relational database systems supporting the same data model. This survey describes and categorizes the inherent differences and nontrivial trade-offs of relevant NRDS classes as well as their commonalities in the context of common design decisions when building such a system with FPGAs. For example, we found in the literature that for keyvalue stores the FPGA should be placed into the system as a smart network interface card (SmartNIC) to benefit from direct access of the FPGA to the network. However, more complex data models and processing of other classes (e. g., graph and document) commonly require more elaborate near-data or socket accelerator placements where the FPGA respectively has the only

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