Parallel Hardware Merge Sorter

Song, Wei; Koch, Dirk; Luján, Mikel; Garside, Jim

doi:10.1109/fccm.2016.34

Cited by 49 publications

(58 citation statements)

References 20 publications

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“…Hardware merge sorter N records can be sorted by recursively using a merge logic. When the merge logic outputs E records per cycle, the total sorting time is roughly estimated to be N E log 2 N cycles [7]. We define W as the number of sorted sequences which a hardware merge sorter can merge simultaneously.…”

Section: Discussionmentioning

confidence: 99%

“…Firstly, we describe the behavior of the E-record merge logic in model (a). Previous work [7] adopts this model. It consists of two sets of FIFOs, two input managers and a merger.…”

Section: Introductionmentioning

confidence: 99%

“…3) We implement, synthesize, and evaluate some hardware merge sorters adopting the proposed architectures on a Virtex-7 VX485T FPGA. The evaluation shows that a hardware merge sorter which can output 32 records per cycle operates at 311MHz and achieves 3.13x higher throughput than the state-of-the-art hardware merge sorter [7].…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

High-Performance Hardware Merge Sorter

Mashimo

Chu

Kise

2017

2017 IEEE 25th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)

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State-of-the-art studies show that FPGA-based hardware merge sorters (HMSs) can achieve superior performance compared with optimized algorithms on CPUs and GPUs. The performance of any HMS is proportional to its operating frequency (F) and the number of records that can be output each cycle (E). However, all existing HMSs have a problem that F drops significantly with increasing E due to the increase of the number of levels of gates. In this paper, we propose novel architectures for HMSs where the number of levels of gates is constant when E is increased. We implement some HMSs adopting the proposed architectures on a Virtex-7 FPGA. The evaluation shows that an HMS of E = 32 operates at 311MHz and achieves 3.13x higher throughput than the state-of-the-art HMS.

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Section: Discussionmentioning

confidence: 99%

“…Firstly, we describe the behavior of the E-record merge logic in model (a). Previous work [7] adopts this model. It consists of two sets of FIFOs, two input managers and a merger.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

High-Performance Hardware Merge Sorter

Mashimo

Chu

Kise

2017

2017 IEEE 25th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)

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“…Up to now, there is no easy way to make hardware sorters run in parallel [17]. Research efforts now-a-days are concentrated on network with minimal depth or number of comparators.…”

Section: Introductionmentioning

confidence: 99%

BulkSort: System Design and Parallel Hardware Implementation Considerations

Ihirri¹,

Errami²,

Khaldoun³

et al. 2019

IJACSA

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Algorithms are commonly perceived as difficult subjects. Many applications today require complex algorithms. However, the researchers look for ways to make them as simple as possible. In high time demanding fields, the process of sorting represents one of the foremost issues in the data structure for searching and optimization algorithms. In parallel processing, we divide program instructions among multiple processors by breaking problems into modules that can be executed in parallel, to reduce the execution time. In this paper, we proposed a novel parallel, re-configurable and adaptive sorting network of the BulkSort algorithm. Our architecture is based on simple and elementary operations such as comparison and binary shifting. The main strength of the proposed solution is the ability to sort in parallel without memory usage. Experimental results show that our proposed model is promising according to the required resources and its ability to perform a high-speed sorting process. In this study, we take into account the analysis result of the Simulink design to establish the required hardware resources of the proposed system.

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“…In [14], a state-of-the-art, scalable parallel merge tree is proposed. The main difference in this model is that instead of assumes a constant sorting rate, it allows a variable sorting rate in the parallel merge-tree.…”

Section: Related Workmentioning

confidence: 99%

Analytical and Experimental Performance Evaluation of Parallel Merge sort on Multicore System

Zaghloul¹,

AlShehri²,

AlJouie³

et al. 2017

IJECS

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Abstract:Parallel programming has evolved due to the availability of fast and inexpensive processors. This technique allows us to determine which portions of an algorithm may be executed simultaneously by exploiting different processors. Recently, the focus has shifted to implementing parallel algorithms on multicore systems in order to increase performance. One of the most common operations performed by computers is sorting, which is a permutation on elements. Merge sort is an effective divide-and conquer sorting algorithm that is easy to understand relative to other sorting strategies. The aim of this paper is to describe and evaluate the performance of the parallel merge sort algorithm over its sequential version using the Java threading application program interface (API) environment, which allows programmers to directly manipulate threads in Java programs. The main idea of the proposed algorithm is to distribute the input data elements into several sub arrays according to the number of threads in each level. The experiments were conducted on a multi-core processor and examined the running time, speedup, efficiency, and scalability. The experiments also tested against different array sizes and different numbers of processors. The experimental results on a multi-core processor show that the proposed parallel algorithm achieves a good performance compared to the sequential algorithm.

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Parallel Hardware Merge Sorter

Cited by 49 publications

References 20 publications

High-Performance Hardware Merge Sorter

High-Performance Hardware Merge Sorter

BulkSort: System Design and Parallel Hardware Implementation Considerations

Analytical and Experimental Performance Evaluation of Parallel Merge sort on Multicore System

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