Parallel implementation of computing-intensive decoding algorithms of H.264 on reconfigurable SoC

Geng, Tongsheng; Liu, Leibo; Yin, Shouyi; Zhu, Min; Jia, Wen; Wei, Shaojun

doi:10.1109/iscas.2010.5537314

Cited by 4 publications

(2 citation statements)

References 8 publications

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“…The decoding programs of H.264, AVS and MPEG-2 are mapped onto the reconfigurable SoC respectively [11] [12], and the testing condition is that the main parts of the SoC work at the frequency of 225MHz and the external memory interface controller works at the frequency of 125MHz. The testing results show that the reconfigurable SoC achieves the performance of real-time decoding of 1920*1080 @ 30fps videos with H.264/AVS/MPEG-2 standards.…”

Section: Soc Antitype Chip and Testing Resultsmentioning

confidence: 99%

Design and implementation of a reconfigurable SoC for high-definition video applications

Sun

Xiangyuan

Liu

et al. 2013

2013 13th International Symposium on Communications and Information Technologies (ISCIT)

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This paper proposes a reconfigurable SoC architecture based on a large-scale reconfigurable processing elements (PEs) array, a high-performance RISC core and several embedded peripherals on-chip, which are coupled tightly through System buses of AMBA2.0. The large-scale PEs array is used to process video signals with different standards under appropriate contexts disposed dynamically. The embedded peripherals are with responsibility for the input of media stream data and output of the decoded multimedia data to display, while the RISC core takes charge of the initialization of the peripherals and the reconfigurable PEs, the pretreatment of media stream data, the audio decoding, the synchronization between audio and video data, and some other scheduling functions. The antitype SoC chip is implemented based on 65nm CMOS silicon techniques, and the testing results show that the reconfigurable SoC achieves the performance of real-time decoding of videos with size of 1920*1080 @ 30fps which follow the H.264, AVS and MPEG-2 standards respectively.

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Section: Soc Antitype Chip and Testing Resultsmentioning

confidence: 99%

Design and implementation of a reconfigurable SoC for high-definition video applications

Sun

Xiangyuan

Liu

et al. 2013

2013 13th International Symposium on Communications and Information Technologies (ISCIT)

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show abstract

“…Like FPGA, CGRA has the flexibility to change its function for different application. Several implementations with CGRA has been proposed in [24], [25] and [26] moreover, CGRA can dynamically configure its computing resource during the execution, so computing resource can be reused, and provide relatively more resource for each step of TBVU to increase the parallelism and reduce total computing time.…”

Section: Related Workmentioning

confidence: 99%

The Implementation of Texture-Based Video Up-Scaling on Coarse-Grained Reconfigurable Architecture

Shi

Yin

Liu

et al. 2015

IEICE Trans. Inf. & Syst.

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SUMMARYVideo Up-scaling is a hotspot in TV display area; as an important brunch of Video Up-scaling, Texture-Based Video Upscaling (TBVU) method shows great potential of hardware implementation. Coarse-grained Reconfigurable Architecture (CGRA) is a very promising processor; it is a parallel computing platform which provides high performance of hardware, high flexibility of software, and dynamical reconfiguration ability. In this paper we propose an implementation of TBVU on CGRA. We fully exploit the characters of TBVU and utilize several techniques to reduce memory I/O operation and total execution time. Experimental results show that our work can greatly reduce the I/O operation and the execution time compared with the non-optimized ones. We also compare our work with other platforms and find great advantage in execution time and resource utilization rate.

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Performance-Conscious Reconfiguration Structure for Large-Scale Coarse-Grained Reconfigurable System

Liu

Gong

Wang

et al. 2015

2015 International Conference on Cyber-Enabled Distributed Computing and Knowledge Discovery

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Parallel implementation of computing-intensive decoding algorithms of H.264 on reconfigurable SoC

Cited by 4 publications

References 8 publications

Design and implementation of a reconfigurable SoC for high-definition video applications

Design and implementation of a reconfigurable SoC for high-definition video applications

The Implementation of Texture-Based Video Up-Scaling on Coarse-Grained Reconfigurable Architecture

Performance-Conscious Reconfiguration Structure for Large-Scale Coarse-Grained Reconfigurable System

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