Parallel Interleaver Design for a High throughput HSPA+/LTE Multi-Standard Turbo Decoder

Abstract

Abstract-To meet the evolving data rate requirements of emerging wireless communication technologies, many parallel architectures have been proposed to implement high throughput turbo decoders. However, concurrent memory reading/writing in parallel turbo decoding architectures leads to severe memory conflict problem, which has become a major bottleneck for high throughput turbo decoders. In this paper, we propose a flexible and efficient VLSI architecture to solve the memory conflict problem for highly parallel turbo decoders targeting multistandard 3G/4G wireless communication systems. To demonstrate the effectiveness of the proposed parallel interleaver architecture, we implemented an HSPA+/LTE/LTE-Advanced multi-standard turbo decoder with a 45nm CMOS technology. The implemented turbo decoder consists of 16 Radix-4 MAP decoder cores, and the chip core area is 2.43 mm 2 . When clocked at 600 MHz, this turbo decoder can achieve a maximum decoding throughput of 826 Mbps in the HSPA+ mode and 1.67 Gbps in the LTE/LTEAdvanced mode, exceeding the peak data rate requirements for both standards.

High performance parallel turbo decoder with configurable interleaving network for LTE application

“…It is noted that all the references except [32] support LTE/LTE-Advanced standard. In addition, multi-standard is supported in [31] with HSPA þ/LTE and in [33] with LTE/WiMAX/DVB-RCS.…”

“…In addition, by appending a special sub-network, the proposed interleaving network can be flexibly extended to support arbitrary contention-free interleavers. Among all the references, [18,22,31] mainly focus on the interleaver design like our work. The multi-stage network from [22,29] introduces a Batcher network based parallel interleaver for high throughput decoding.…”

“…However, the network has to be reconstructed when different level of parallelism is required. In [31], a double-buffer contention-free architecture is proposed to solve the memory conflicts problem in HSPA þ standard. Although an unified architecture is presented to support both HSPA þ and LTE, it needs multiple QPP network to support higher parallelism and costs large control logic and memory.…”

“…Although an unified architecture is presented to support both HSPA þ and LTE, it needs multiple QPP network to support higher parallelism and costs large control logic and memory. Comparatively, our work has 73% less memory than [31]. A low complexity address generator using QPP recursive property is given in [18].…”

“…This work TCAS-I 2014 [29] TCAS-I 2014 [30] TCAS-I 2014 [31] JSSC 2013 [32] DATE 2013 [33] ISTC 2012 [15] Integration 2011 [18] JSSC 2011 [22] Standard ( …”