Parallel Logic Simulation: Myth or Reality?

Chang, Kuo–En; Browy, Chris

doi:10.1109/mc.2011.385

Cited by 15 publications

(8 citation statements)

References 4 publications

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“…The use of hardware to assist simulation such as Field Programmable Gate Array (FPGA), Graphical Processing Unit (GPU) and custom hardware emulators has emerged. However, these hardware assisted simulators are limited in what they can simulate, are quite expensive, hard to set up, require partitioning of the design, have lengthy design compilation time and suffer from reduced signal controllability and observability making it harder to debug a design [1][5] [13]. Companies designing Systems on a Chip (SoC) still use hardware assisted simulation because of time to market pressure but this approach is not viable for companies with limited budget [4].…”

Section: A Current Verification Trendsmentioning

confidence: 99%

Fast time-parallel C-based event-driven RTL simulation

Ahmad

Ciesielski

2014

17th International Symposium on Design and Diagnostics of Electronic Circuits &Amp; Systems

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Abstract-Simulation of the RTL model is one of the first and mandatory steps of the design verification flow. Such a simulation needs to be repeated often due to the changing nature of the design in its early development stages and after consecutive bug fixing. Despite its relatively high level of abstraction, RTL simulation is a very time consuming process, often requiring nightly or week-long regression runs. In this work, we propose an original approach to accelerating RTL simulation that leverages parallelism offered by multi-core machines. However, in contrast to traditional, parallel distributed RTL simulation, the proposed method accelerates RTL simulation in temporal domain by dividing the entire simulation run into independent simulation slices, each to be run on a separate core. It is combined with fast simulation model at ESL level that provides the required initial state for each independent simulation slice. The paper describes the basic idea of the method and provides some initial experimental results showing its effectiveness in improving RTL simulation performance in an automated way.

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Section: A Current Verification Trendsmentioning

confidence: 99%

Fast time-parallel C-based event-driven RTL simulation

Ahmad

Ciesielski

2014

17th International Symposium on Design and Diagnostics of Electronic Circuits &Amp; Systems

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“…Chatterjee [14] proposed the parallel event-driven gate level simulation using general purpose GPUs (Graphic Processing Units). However, it lacks debugging and the proposed simulation flow cannot be integrated into the existing ASIC/FPGA design flow seamlessly [1]. Zhu et al [15] developed a distributed algorithm for GPUs that can handle arbitrary delays, but still suffers from heavy synchronization and communication overhead inherent to all distributed simulation techniques.…”

Section: Previous Workmentioning

confidence: 99%

“…Unfortunately, it has not been very successful for a number of reasons: i) difficulty in design partitioning and load balancing; ii) communication overhead between partitions; iii) synchronization overhead imposed by the distributed environment; and iv) lack of concurrency in the design. Readers are recommended to review the recent papers [1][2] on the scope of parallel multi-core simulation.…”

Section: Introduction To Design Verification Approachesmentioning

confidence: 99%

An Approach to Multi-core Functional Gate-Level Simulation Minimizing Synchronization and Communication Overheads

Ahmad

Ciesielski

2013

2013 14th International Workshop on Microprocessor Test and Verification

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This paper addresses performance issues encountered in parallel functional gate-level simulation executed on multi-core machine. It demonstrates that a straightforward application of the multi-core simulation on a multi-core machine does not improve simulation performance. This is due to unbalanced partitioning, lack of sufficient concurrency in the design partitions, overhead due to communication between partitions, and synchronization overhead imposed by the simulator. We propose, implement and automate a generic (partitioning-independent) prediction-based solution to eliminate or minimize communication and synchronization overhead in an event-driven functional gate-level simulation on a multi-core machine. We demonstrate speedup obtained with this method on a set of real Opensource designs.

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“…Parallel event-driven logic simulation has been proposed to alleviate the low performance of sequential simulation [2][3] [4][5] [6]. Unfortunately, it had been not successful because of; i) difficulty in design partitioning, ii) heavy synchronization and communication overhead among partitioned modules, especially in gate-level timing simulation, and iii) load balancing among the distributed simulation jobs [7]. A very different distributed parallel event-driven simulation method based on the prediction had been proposed [8].…”

Section: Introductionmentioning

confidence: 99%

Predictive Parallel Gate-level Timing Simulation with Fast and Accurate Prediction

Han¹,

Yang²

2017

World Congress on Electrical Engineering and Computer Systems and Science

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-A promising predictive parallel event-driven logic simulation had been proposed for greatly enhancing the parallel simulation performance, which could be heavily disturbed by synchronization & communication overhead among local simulations. For achieving the maximal simulation performance in the predictive parallel event-driven logic simulation, the high prediction accuracy is the key factor. In this paper, we have enhanced this noble parallel simulation method with fast, yet accurate prediction using incremental simulation. Preliminary experimentation has been performed for common design changes, and shown the effectiveness of the proposed approach.

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Parallel Logic Simulation: Myth or Reality?

Cited by 15 publications

References 4 publications

Fast time-parallel C-based event-driven RTL simulation

Fast time-parallel C-based event-driven RTL simulation

An Approach to Multi-core Functional Gate-Level Simulation Minimizing Synchronization and Communication Overheads

Predictive Parallel Gate-level Timing Simulation with Fast and Accurate Prediction

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