Parallel optical interconnects with mixed-signal OEIC and fibre arrays for high-speed communication

Abstract

We present a system for direct parallel optical data communication between integrated circuits on neighboured printed circuit boards based on a monolithic integrated CMOS smart pixel array, fibre arrays, and VCSELs. The advantage of our system versus backplane systems is the direct data transfer through the space avoiding planar and area consuming interconnections. The detector chip allows a data rate of 625 Mbit/s per link and is cycled by an optical clock. A simulation of the chip layout showed 260 % more performance versus electrical off-chip interconnects. In principle an 8×8 data transfer is feasible allowing a data rate of 40 Gbit/s. The detector combines an optical receiver array with a digital processor array which executes image processing algorithms. The optical receiver is formed by a PIN photodiode with a diameter of 40 µm, a transimpedance amplifier (TIA) and a decision-making postamplifier. The measured responsivity of the photodiode without antireflection coating is R=0.382 A/W at an optical wavelength of 670 nm. The TIA consists of a CMOS inverter and a PMOS transistor forming the feedback resistor. Together with the postamplifier, formed by a chain of five CMOS inverters and attaining digital CMOS levels, a data rate of 625 Mbit/s is achieved.

Geometric computation with smart pixels

“…We call such a unit a "smart pixel." Abstract and futuristic as it may sound, this hardware already exists in small grid sizes [3], and algorithms for various geometric problems are presented in [1] and [2]. Smart pixels allow for massively parallel computations that can be used to create sublinear algorithms for many common tasks.…”

Marching-pixels

“…An edge detection algorithm and some morphological operations are hardwired implemented in the chip. Details concerning the realization and the architecture of this chip can be found in [15], [16], [17]. This chip represents a valuable preparatory work for a future realization of our marching pixels concept (see also outlook in section 5).…”

Reconfigurable On-Chip SIMD Processor Architectures for Intelligent CMOS Camera Chips

“…The analogue part was designed by the Institute of Electrical Measurement and Circuit Design of Vienna University of Technology, the digital part was designed by us [10]. The chip was realized with a XB06P3-BiCMOS technology of XFAB company in Erfurt, Germany.…”

“…In this way we can test the optical functionality of our chip. More details concerning the implementation of the digital and analogue part as well as the comparator circuit can be found in [10] and [11]. photo diode digital logic test structure…”