Parallel Programming for FPGAs

Kastner, Ryan; Matai, Janarbek; Neuendorffer, Stephen

doi:10.48550/arxiv.1805.03648

Cited by 12 publications

(21 citation statements)

References 31 publications

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“…At a high level, an FPGA can be described as an array of programmable logic blocks and programmable interconnect between those blocks that can be configured after fabrication to implement arbitrary program logic. 88 An example of an Intel FPGA (formerly Altera) architecture is shown in Figure 6.The Adaptive Logic Modules (ALMs) are the fundamental compute units of an FPGA. ALMs consist of a Lookup table (LUT) which is a memory that maps address signals as inputs and the outputs are stored in the corresponding memory entries.…”

Section: Reconfigurable Architectures For MDmentioning

confidence: 99%

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Accelerators for Classical Molecular Dynamics Simulations of Biomolecules

Jones

Allen

Yang

et al. 2022

J. Chem. Theory Comput.

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Atomistic Molecular Dynamics (MD) simulations provide researchers the ability to model biomolecular structures such as proteins and their interactions with drug-like small molecules with greater spatiotemporal resolution than is otherwise possible using experimental methods. MD simulations are notoriously expensive computational endeavors that have traditionally required massive investment in specialized hardware to access biologically relevant spatiotemporal scales. Our goal is to summarize the fundamental algorithms that are employed in the literature to then highlight the challenges that have affected accelerator implementations in practice. We consider three broad categories of accelerators: Graphics Processing Units (GPUs), Field-Programmable Gate Arrays (FPGAs), and Application Specific Integrated Circuits (ASICs). These categories are comparatively studied to facilitate discussion of their relative trade-offs and to gain context for the current state of the art. We conclude by providing insights into the potential of emerging hardware platforms and algorithms for MD.

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Section: Reconfigurable Architectures For MDmentioning

confidence: 99%

“…ALMs consist of a Lookup table (LUT) which is a memory that maps address signals as inputs and the outputs are stored in the corresponding memory entries. 88 LUTs can be programmed to compute any n-input Boolean function. Full Adders perform addition and subtraction of binary inputs.…”

Section: Reconfigurable Architectures For MDmentioning

confidence: 99%

Accelerators for Classical Molecular Dynamics Simulations of Biomolecules

Jones

Allen

Yang

et al. 2022

J. Chem. Theory Comput.

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“…In order to build the Huffman tree, we must sort the symbols based on their frequencies after we filter out symbols with a frequency of zero. Previous works [26,51] use radix sort to reduce the utilization of hardware resources. However, we find that radix sort typically takes more than 30% of the total time when we break down the execution time of generating codewords.…”

Section: Efficient and Adaptive Huffman Codermentioning

confidence: 99%

Ceaz

Zhang

Jin

Geng

et al. 2022

Proceedings of the 36th ACM International Conference on Supercomputing

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As HPC systems continue to grow to exascale, the amount of data that needs to be saved or transmitted is exploding. To this end, many previous works have studied using error-bounded lossy compressors to reduce the data size and improve the I/O performance. However, little work has been done for effectively offloading lossy compression onto FPGA-based SmartNICs to reduce the compression overhead. In this paper, we propose a hardware-algorithm codesign for an efficient and adaptive lossy compressor for scientific data on FPGAs (called CEAZ), which is the first lossy compressor that can achieve high compression ratios and throughputs simultaneously. Specifically, we propose an efficient Huffman coding approach that can adaptively update Huffman codewords online based on codewords generated offline, from a variety of representative scientific datasets. Moreover, we derive a theoretical analysis to support a precise control of compression ratio under an errorbounded compression mode, enabling accurate offline Huffman codewords generation. This also helps us create a fixed-ratio compression mode for consistent throughput. In addition, we develop an efficient compression pipeline by adopting cuSZ's dual-quantization algorithm to our hardware use cases. Finally, we evaluate CEAZ on five real-world datasets with both a single FPGA board and 128 nodes (to accelerate parallel I/O). Experiments show that CEAZ outperforms the second-best FPGA-based lossy compressor by 2.3× of throughput and 3.0× of ratio. It also improves MPI_File_write and MPI_Gather throughputs by up to 28.9× and 37.8×, respectively. CCS CONCEPTS• Computer systems organization → Reconfigurable computing.

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“…Therefore, to realize a high degree of parallelism required in protocol sized LDPC codes, many BRAMs must be used in parallel to access the BP LLRs. Furthermore to meet FPGA device timing constraints, today's dualported support for BRAMs limits the size of a single data access to 2,048 bits and the number of BRAMs accessible in a single clock cycle to 1,024 [37,68,74]. This limitation results in the maximum degree of achievable parallelization in current top-end Xilinx FP-GAs, which corresponds to a 2,048 (1,024 × 2) LDPC code block length.…”

Section: Classical Bp Decoder Limitationsmentioning

confidence: 99%

Towards quantum belief propagation for LDPC decoding in wireless networks

Kasi

Jamieson

2020

Proceedings of the 26th Annual International Conference on Mobile Computing and Networking

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We present Quantum Belief Propagation (QBP), a Quantum Annealing (QA) based decoder design for Low Density Parity Check (LDPC) error control codes, which have found many useful applications in Wi-Fi, satellite communications, mobile cellular systems, and data storage systems. QBP reduces the LDPC decoding to a discrete optimization problem, then embeds that reduced design onto quantum annealing hardware. QBP's embedding design can support LDPC codes of block length up to 420 bits on real state-ofthe-art QA hardware with 2,048 qubits. We evaluate performance on real quantum annealer hardware, performing sensitivity analyses on a variety of parameter settings. Our design achieves a bit error rate of 10 −8 in 20 µs and a 1,500 byte frame error rate of 10 −6 in 50 µs at SNR 9 dB over a Gaussian noise wireless channel. Further experiments measure performance over real-world wireless channels, requiring 30 µs to achieve a 1,500 byte 99.99% frame delivery rate at SNR 15-20 dB. QBP achieves a performance improvement over an FPGA based soft belief propagation LDPC decoder, by reaching a bit error rate of 10 −8 and a frame error rate of 10 −6 at an SNR 2.5-3.5 dB lower. In terms of limitations, QBP currently cannot realize practical protocol-sized (e.g., Wi-Fi, WiMax) LDPC codes on current QA processors. Our further studies in this work present future cost, throughput, and QA hardware trend considerations. CCS CONCEPTS• Networks → Wireless access points, base stations and infrastructure; • Hardware → Quantum computation.

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Parallel Programming for FPGAs

Cited by 12 publications

References 31 publications

Accelerators for Classical Molecular Dynamics Simulations of Biomolecules

Accelerators for Classical Molecular Dynamics Simulations of Biomolecules

Ceaz

Towards quantum belief propagation for LDPC decoding in wireless networks

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