1987
DOI: 10.1007/3-540-17945-3_16
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Parallel programming in Temporal Logic

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Cited by 14 publications
(13 citation statements)
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“…This is a useful technique in re-discovery of topology in large and complex SCADA systems, where a traditional network scanner can cause PLC failure in the form of a DOS attack. Hale (1988). Their solution was tested using a Siemens S7-1200 PLC with the Arduino connected to the Profinet interface.…”
Section: Runtime Verification Of Scadamentioning
confidence: 99%
“…This is a useful technique in re-discovery of topology in large and complex SCADA systems, where a traditional network scanner can cause PLC failure in the form of a DOS attack. Hale (1988). Their solution was tested using a Siemens S7-1200 PLC with the Arduino connected to the Profinet interface.…”
Section: Runtime Verification Of Scadamentioning
confidence: 99%
“…In this section we revisit the standard semantics of Interval Temporal Logic [15] (albeit restricted to the finite case) ITL is the underlying formalism of the AnaTempura Runtime Verification Framework [29] which uses an executable subset of ITL called Tempura developed by [40,41].…”
Section: Syntax and Informal Semanticsmentioning
confidence: 99%
“…The model can be implemented straightforwardly from its semantics using AnaTempura [10], [5], resulting in the following code for example 1: Here three events are modelled for the service, and an example trace is generated by the function evtmodel(Evts). AnaTempura can be run in a run-time verification mode and could receive these events from an external program.…”
Section: Fig 5: Policy Rule Evaluationmentioning
confidence: 99%