Parallel Programming Model for the Epiphany Many-Core Coprocessor Using Threaded MPI

Ross, James A.; Richie, David A.; Park, Song J.; Shires, Dale R.

doi:10.1145/2768177.2768183

Cited by 12 publications

(18 citation statements)

References 15 publications

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“…An NoC-based MPSoC is explored for some IP/CV algorithms in [12]. The authors use an MPI (message passing interface) to parallelize the algorithms and distribute the threads among the cores.…”

Section: Ip/cv Systemsmentioning

confidence: 99%

A Manycore Vision Processor for Real-Time Smart Cameras

Silva

Lima

Arias-García

et al. 2021

Sensors

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Real-time image processing and computer vision systems are now in the mainstream of technologies enabling applications for cyber-physical systems, Internet of Things, augmented reality, and Industry 4.0. These applications bring the need for Smart Cameras for local real-time processing of images and videos. However, the massive amount of data to be processed within short deadlines cannot be handled by most commercial cameras. In this work, we show the design and implementation of a manycore vision processor architecture to be used in Smart Cameras. With massive parallelism exploration and application-specific characteristics, our architecture is composed of distributed processing elements and memories connected through a Network-on-Chip. The architecture was implemented as an FPGA overlay, focusing on optimized hardware utilization. The parameterized architecture was characterized by its hardware occupation, maximum operating frequency, and processing frame rate. Different configurations ranging from one to eighty-one processing elements were implemented and compared to several works from the literature. Using a System-on-Chip composed of an FPGA integrated into a general-purpose processor, we showcase the flexibility and efficiency of the hardware/software architecture. The results show that the proposed architecture successfully allies programmability and performance, being a suitable alternative for future Smart Cameras.

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Section: Ip/cv Systemsmentioning

confidence: 99%

A Manycore Vision Processor for Real-Time Smart Cameras

Silva

Lima

Arias-García

et al. 2021

Sensors

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“…The programming of these micro-cores is technically challenging, with both technologies supporting C via the GCC tool chain. Whilst some approaches beyond using C with the low level hardware specific library, such as OpenCL [15], BSP [16], OpenMP [17] and MPI [18] have been developed, these are at different levels of maturity and still require the programmer to explicitly program the chip using C at a very low level. Indeed, Xilinx's Pynq-II board has been designed around ease of use, loading up a default configuration of three MicroBlaze cores, and presenting a Python interface via the Jupyter notebook.…”

Section: Background and Related Workmentioning

confidence: 99%

High level programming abstractions for leveraging hierarchical memories with micro-core architectures

Jamieson

Brown²

2020

Journal of Parallel and Distributed Computing

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Micro-core architectures combine many low memory, low power computing cores together in a single package. These are attractive for use as accelerators but due to limited on-chip memory and multiple levels of memory hierarchy, the way in which programmers offload kernels needs to be carefully considered. In this paper we use Python as a vehicle for exploring the semantics and abstractions of higher level programming languages to support the offloading of computational kernels to these devices. By moving to a pass by reference model, along with leveraging memory kinds, we demonstrate the ability to easily and efficiently take advantage of multiple levels in the memory hierarchy, even ones that are not directly accessible to the micro-cores. Using a machine learning benchmark, we perform experiments on both Epiphany-III and MicroBlaze based micro-cores, demonstrating the ability to compute with data sets of arbitrarily large size. To provide context of our results, we explore the performance and power efficiency of these technologies, demonstrating that whilst these two micro-core technologies are competitive within their own embedded class of hardware, there is still a way to go to reach HPC class GPUs.

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“…Threaded MPI is a compact version of MPI for the Epiphany coprocessor architecture [4], which we have previously demonstrated for several image processing tasks [5]. Threaded MPI uses coprocessor semantics to access the resources on the Epiphany RISC cores.…”

Section: Threaded Mpimentioning

confidence: 99%

“…The MPI code that runs on the Epiphany architecture is written as a thread in a separate kernel, and that uses Pthread semantics for passing arguments. The host code can make the call to coprthr_mpiexec( ) multiple times within the main code, and the code can employ multiple MPI kernels [4].…”

Section: Threaded Mpimentioning

confidence: 99%

Implementing Hilbert transform for Digital Signal Processing on epiphany many-core coprocessor

Labowski

Jungwirth

Ross

et al. 2016

2016 IEEE High Performance Extreme Computing Conference (HPEC)

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The Adapteva Epiphany MIMD architecture is a scalable 2D array of RISC cores with a fast network-on-chip (NoC) for parallel processing. The work presented here discusses the suitability of the architecture to handle software defined radio (SDR) applications such as Finite Impulse Response (FIR) filters. This paper discusses implementation of the Hilbert filter through using the COPRTHR 2.0 SDK which includes Pthreadlike interface for offloading the thread function. We present timing and performance results for our implementation.

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Parallel Programming Model for the Epiphany Many-Core Coprocessor Using Threaded MPI

Cited by 12 publications

References 15 publications

A Manycore Vision Processor for Real-Time Smart Cameras

A Manycore Vision Processor for Real-Time Smart Cameras

High level programming abstractions for leveraging hierarchical memories with micro-core architectures

Implementing Hilbert transform for Digital Signal Processing on epiphany many-core coprocessor

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