2010
DOI: 10.1016/j.engappai.2009.12.001
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Parallel scalable hardware implementation of asynchronous discrete particle swarm optimization

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Cited by 29 publications
(14 citation statements)
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“…Although this approach has more flexibility, improvement in the execution speed is less. Later, an architecture for PSO algorithm was proposed in which an on-chip multiprocessing based on system-on-a-programmable-chip (SOPC) methodology is used to realize the PSO algorithm [16]. Later a hardware accelerator for PSO algorithm was reported [18] and validated its [20].…”
Section: Literature Surveymentioning
confidence: 99%
“…Although this approach has more flexibility, improvement in the execution speed is less. Later, an architecture for PSO algorithm was proposed in which an on-chip multiprocessing based on system-on-a-programmable-chip (SOPC) methodology is used to realize the PSO algorithm [16]. Later a hardware accelerator for PSO algorithm was reported [18] and validated its [20].…”
Section: Literature Surveymentioning
confidence: 99%
“…The digital circuits act as the controller that provides a time sequence of signals for initiating the operations in the data path and also determine the next state of the control sub system. A pipelined architecture is required for computational operations of algorithms [28]. The pipeline level and the schedules of neural-controller computation process flow are given in Table 4 and the pipeline stages are marked (lower case letter) in Fig.…”
Section: Design Approach and Behavioral Modeling Of Neural-controllermentioning
confidence: 99%
“…It also contains some memory blocks used to keep vectors and values of PSO such as particle location, particle velocity, and pbest vectors. The internal structure of the core can be found in [5,6]. Location vectors of particles (weights) are updated using this core.…”
Section: Pso Corementioning
confidence: 99%