Parallel tree contraction and prefix computations on a large family of interconnection topologies

Hsu, Wen Jing; Page, Carl V.

doi:10.1007/bf01177744

Cited by 11 publications

(3 citation statements)

References 9 publications

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“…There have been many parallel algorithms designed for summing andÂor prefix summing on various parallel modelsÂmachines, including PRAM [2, 6, 9 11, 17, 18], binary tree [12], hypercube [7,19], and others [4,5,7,13,14]. However, the focus of this paper is not only on efficient algorithm design, but on overall time complexity.…”

Section: Introductionmentioning

confidence: 99%

Optimal and Efficient Algorithms for Summing and Prefix Summing on Parallel Machines

Santos

2002

Journal of Parallel and Distributed Computing

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Section: Introductionmentioning

confidence: 99%

Optimal and Efficient Algorithms for Summing and Prefix Summing on Parallel Machines

Santos

2002

Journal of Parallel and Distributed Computing

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“…, x n , and for a binary associative operation *, the prefix computation of the sequence is defined as outputs y i , 1 ≤ i ≤ n, y i = x 1 * x 2 * · · · * x i . Numbers of parallel prefix combinational structures have been proposed over the past years [4][5][6][7][8][9][10][11][12][13][14][15]. These combinational circuits intend to optimize area and speed through having circuits of minimum depth and/or size [16,17] (the depth of a circuit is the number of levels in the circuit, while the size is the number of operation nodes in the circuit).…”

mentioning

confidence: 99%

Dynamic-width reconfigurable parallel prefix circuits

El-Boghdadi

2015

J Supercomput

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Parallel prefix circuits have drawn high interest because of their importance in many applications such as fast adders. Most proposed parallel prefix circuits assume fixed width. The input size could be of the same width as the circuit or different than the width of the circuit. In this paper, we propose a class of reconfigurable parallel prefix circuits,Ř-circuits, that support different operational modes. TheŘ-circuit can be reconfigured as one parallel prefix circuit of high width as well as several smaller width parallel prefix circuits that can operate on different prefix problems in parallel. In particular, anŘ-circuit,Ř(k(m)), of width km with k building blocks (slices) each of width m, can be configured as a number of z prefix circuits, z ≤ k, each of width b j , such that z j=1 b j = km. For a circuit C R b ∈Ř(k(m)) of b slices and width bm, we show how such circuit can be constructed. We derive a bound for the depth of C R b and show how C R b can handle input size n ≥ bm. Then, we show the performance ofŘ(k(m)) and compare it with other fixed same-width prefix circuits.

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“…Fibonacci Cubes use fewer links than comparable hypercubes and their size does not increase as fast as hypercubes. The structural analysis of the Fibonacci Cube has been extensively studied in [2] and its applications in [9]. A Fibonacci Cube can also be viewed as resulting from a complete hypercube after some nodes become faulty and the system is reconfigured.…”

Section: Introductionmentioning

confidence: 99%

Extended Fibonacci cubes

Proceedings.Seventh IEEE Symposium on Parallel and Distributed Processing

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Abstract-The Fibonacci Cube is an interconnection network that possesses many desirable properties that are important in network design and application. The Fibonacci Cube can efficiently emulate many hypercube algorithms and uses fewer links than the comparable hypercube, while its size does not increase as fast as the hypercube. However, most Fibonacci Cubes (more than 2/3 of all) are not Hamiltonian. In this paper, we propose an Extended Fibonacci Cube (EFC 1 ) with an even number of nodes. It is defined based on the same sequence F(i ) = F(i -1) + F(i -2) as the regular Fibonacci sequence; however, its initial conditions are different. We show that the Extended Fibonacci Cube includes the Fibonacci Cube as a subgraph and maintains its sparsity property. In addition, it is Hamiltonian and is better in emulating other topologies. Specifically, the Extended Fibonacci Cube can embed binary trees more efficiently than the regular Fibonacci Cube and is almost as efficient as the hypercube, even though the Extended Fibonacci Cube is a much sparser network than the hypercube. We also propose a series of Extended Fibonacci Cubes with even number of nodes. Any Extended Fibonacci Cube (EFC k , with k ≥ 1) in the series contains the node set of any other cube that precedes EFC k in the series. We show that any Extended Fibonacci Cube maintains virtually all the desirable properties of the Fibonacci Cube. The EFC k s can be considered as flexible versions of incomplete hypercubes, which eliminates their restriction on the number of nodes, and, thus, makes it possible to construct parallel machines with arbitrary sizes.

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Parallel tree contraction and prefix computations on a large family of interconnection topologies

Cited by 11 publications

References 9 publications

Optimal and Efficient Algorithms for Summing and Prefix Summing on Parallel Machines

Optimal and Efficient Algorithms for Summing and Prefix Summing on Parallel Machines

Dynamic-width reconfigurable parallel prefix circuits

Extended Fibonacci cubes

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