Parallel VLSI algorithm for stable inversion of dense matrices

El-Amawy, A.; Dharmarajan, K.R.

doi:10.1049/ip-e.1989.0079

Cited by 43 publications

(37 citation statements)

References 6 publications

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“…(12) are used to generate the results of stage 2 and 3, respectively, and the results of stage 4 uses Eq. (10). As shown in the equations, there are more than two terms in matrix expression such that we can use carry save adder (CSA) to compute add operation.…”

Section: Sign-select Lookahead Cordic Architecturementioning

confidence: 99%

“…Recently, QR decomposition with Givens rotation [10] is widely adopted in matrix inversion for MIMO receivers [11][12][13], as it can be efficiently implemented using simple coordinate rotation digital computer (CORDIC) module. Since it was first proposed in 1959 [14], the CORDIC has been widely used to calculate the trigonometric functions in digital signal processing (DSP) systems.…”

Section: Introductionmentioning

confidence: 99%

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Sign-Select Lookahead CORDIC based High-Speed QR Decomposition Architecture for MIMO Receiver Applications

Lee¹

2011

JSTS:Journal of Semiconductor Technology and Science

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Abstract-This paper presents a high-speed QR decomposition architecture for the multi-input-multioutput (MIMO) receiver based on Givens rotation. Under fast-varying channel, since the inverse matrix calculation has to be performed frequently in MIMO receiver, a high performance and low latency QR decomposition module is highly required. The proposed QR decomposition architecture is composed of Sign-Select Lookahead (SSL) coordinate rotation digital computer (CORDIC). In the SSL-CORDIC, the sign bits, which are computed ahead to select which direction to rotate, are used to select one of the last iteration results, therefore, the data dependencies on the previous iterations are efficiently removed. Our proposed QR decomposition module is implemented using TSMC 0.25 µm CMOS process. Experimental results show that the proposed QR architecture achieves 34.83% speed-up over the Compact CORDIC based architecture for the 4 × 4 matrix decomposition.

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Section: Sign-select Lookahead Cordic Architecturementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Sign-Select Lookahead CORDIC based High-Speed QR Decomposition Architecture for MIMO Receiver Applications

Lee¹

2011

JSTS:Journal of Semiconductor Technology and Science

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“…Since all PEs can work simultaneously, the latency is shorter than with a single processor system, and the results of D are outputted in parallel. Systolic algorithms and the corre-sponding systolic arrays have been designed for a number of linear algebra algorithms, such as matrix triangularization [20], matrix inversion [21] , adaptive nulling [22], recursive leastsquare [23], [24], etc. An overview of systolic designs for several computationally demanding linear algebra algorithms for signal processing and communications applications was recently published in [25].…”

Section: Introductionmentioning

confidence: 99%

Systolic arrays for lattice-reduction-aided mimo detection

2011

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Abstract-Multiple-input, multiple-output (MIMO) technology provides high data rate and enhanced QoS for wireless communications. Since the benefits from MIMO result in a heavy computational load in detectors, the design of low-complexity sub-optimum receivers is currently an active area of research. Lattice-reduction-aided detection (LRAD) has been shown to be an effective low-complexity method with near-ML performance. In this paper we advocate the use of systolic array architectures for MIMO receivers, and in particular we exhibit one of them based on LRAD. The "LLL lattice reduction algorithm" and the ensuing linear detections or successive spatial-interference cancellations can be located in the same array, which is considerably hardware-efficient. Since the conventional form of the LLL algorithm is not immediately suitable for parallel processing, two modified LLL algorithms are considered here for the systolic array. LLL algorithm with full-size reduction (FSR-LLL) is one of the versions more suitable for parallel processing. Another variant is the all-swap lattice-reduction (ASLR) algorithm for complex-valued lattices, which processes all lattice basis vectors simultaneously within one iteration. Our novel systolic array can operate both algorithms with different external logic controls. In order to simplify the systolic array design, we replace the Lovász condition in the definition of LLL-reduced lattice with the looser Siegel condition. Simulation results show that for LRaided linear detections, the bit-error-rate performance is still maintained with this relaxation. Comparisons between the two algorithms in terms of bit-error-rate performance, and average FPGA processing time in the systolic array are made, which shows that ASLR is a better choice for a systolic architecture, especially for systems with a large number of antennas.

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“…The algorithms, namely the coordinate rotation digital computation (CORDIC) [6] algorithm and the squared Givens rotation (SGR) [7] algorithm, are applied to compute the QR decomposition (QRD) via Givens rotations. Then the matrix inversion is obtained by using a triangular matrix inversion algorithm [8] or a back substitution algorithm [4]. Two detector architectures, based on these algorithms and systolic array structures [9], [10], are designed for a 2 x 2 MIMO-OFDM system and implemented in a field programmable gate array (FPGA) chip.…”

Section: Introductionmentioning

confidence: 99%

“…In this paper, two square root free methods based on QRD via Givens rotations are considered for calculation of the matrix inversion in (2): * The CORDIC [6] + the back substitution [4] algorithms * The SGR [7] + triangular matrix inversion [8] algorithms For more details, see [12].…”

Section: Introductionmentioning

confidence: 99%