Parallelism-Aware Memory Interference Delay Analysis for COTS Multicore Systems

Yun, Heechul; Pellizzon, Rodolfo; Valsan, Prathap Kumar

doi:10.1109/ecrts.2015.24

Cited by 68 publications

(41 citation statements)

References 36 publications

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“…Consequently, the access latency to the LLC is fixed, and equals to 50 cycles (L acc = 50 cycles). The DRAM access overheads can be computed using other approaches such as [20] [21], and they are additive [28] (f) Intra-core coherence latency for the synthetic workloads. to other core requests.…”

Section: Discussionmentioning

confidence: 99%

Predictable Cache Coherence for Multi-core Real-Time Systems

Hassan

Kaushik

Patel

2017

2017 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS)

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Abstract-This work addresses the challenge of allowing simultaneous and predictable accesses to shared data on multi-core systems. We accomplish this by proposing a predictable cache coherence protocol, which mandates the use of certain invariants to ensure predictability. In particular, we enforce these invariants by augmenting the classic modify-share-invalid (MSI) protocol with transient coherence states, and minimal architectural changes. This allows us to derive worst-case latency bounds on predictable MSI (PMSI) protocol. Our analysis shows that while the arbitration latency scales linearly, the coherence latency scales quadratically with the number of cores. We implement PMSI in gem5, and execute SPLASH-2 and synthetic multi-threaded workloads. Our empirical results show that our approach is always within the analytical worst-case latency bounds, and that PMSI improves average-case performance by up to 4× over the next best predictable alternative. PMSI has average slowdowns of 1.45× and 1.46× compared to conventional MSI and MESI protocols, respectively.

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Section: Discussionmentioning

confidence: 99%

Predictable Cache Coherence for Multi-core Real-Time Systems

Hassan

Kaushik

Patel

2017

2017 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS)

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“…To quantify memory interference on DRAM-banks, [19,27] proposed two analyses, request-driven and job-driven. The former one bounds memory request delays considering memory interference on the DRAM bank, while the latter adds the worst-case concurrency on the data-bus of the DRAM.…”

Section: Related Workmentioning

confidence: 99%

Tightening Contention Delays While Scheduling Parallel Applications on Multi-core Architectures

Rouxel

Derrien

Puaut

2017

ACM Trans. Embed. Comput. Syst.

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Multi-core systems are increasingly interesting candidates for executing parallel real-time applications, in avionic, space or automotive industries, as they provide both computing capabilities and power efficiency. However, ensuring that timing constraints are met on such platforms is challenging, because some hardware resources are shared between cores.Assuming worst-case contentions when analyzing the schedulability of applications may result in systems mistakenly declared unschedulable, although the worst-case level of contentions can never occur in practice. In this paper, we present two contention-aware scheduling strategies that produce a time-triggered schedule of the application's tasks. Based on knowledge of the application's structure, our scheduling strategies precisely estimate the effective contentions, in order to minimize the overall makespan of the schedule. An Integer Linear Programming (ILP) solution of the scheduling problem is presented, as well as a heuristic solution that generates schedules very close to ones of the ILP (5 % longer on average), with a much lower time complexity. Our heuristic improves by 19% the overall makespan of the resulting schedules compared to a worst-case contention baseline.

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“…Kim et al who also include shared banks relax this limitation. Yun et al [103] study interference arising in COTS platforms that can generate multiple outstanding memory requests and evaluate their approach on a simulation platform.…”

Section: Shared Memory Banksmentioning

confidence: 99%

Timing Predictability in Future Multi-Core Avionics Systems

Löfwenmark¹

2017

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With more functionality added to safety-critical avionics systems, new platforms are required to offer the computational capacity needed. Multi-core platforms offer a potential that is now being explored, but they pose significant challenges with respect to predictability due to shared resources (such as memory) being accessed from several cores in parallel. Multi-core processors also suffer from higher sensitivity to permanent and transient faults due to shrinking transistor sizes.This thesis addresses several of these challenges. First, we review major contributions that assess the impact of fault tolerance on worst-case execution time of processes running on a multi-core platform. In particular, works that evaluate the timing effects using fault injection methods. We conclude that there are few works that address the intricate timing effects that appear when inter-core interferences due to simultaneous accesses of shared resources are combined with the fault tolerance techniques. We assess the applicability of the methods to COTS multi-core processors used in avionics. We identify dark spots on the research map of the joint problem of hardware reliability and timing predictability for multi-core avionics systems.Next, we argue that the memory requests issued by the real-time operating systems (RTOS) must be considered in resource-monitoring systems to ensure proper execution on all cores.We also adapt and extend an existing method for worst-case response time analysis to fulfill the specific requirements of avionics systems. We relax the requirement of private memory banks to also allow cores to share memory banks.

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Parallelism-Aware Memory Interference Delay Analysis for COTS Multicore Systems

Cited by 68 publications

References 36 publications

Predictable Cache Coherence for Multi-core Real-Time Systems

Predictable Cache Coherence for Multi-core Real-Time Systems

Tightening Contention Delays While Scheduling Parallel Applications on Multi-core Architectures

Timing Predictability in Future Multi-Core Avionics Systems

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